没有合适的资源?快使用搜索试试~ 我知道了~
A high resolution low power ADC,multi-channel sensor
资源推荐
资源详情
资源评论
LMP90100/LMP90099/
LMP90098/LMP90097
July 25, 2011
Sensor AFE System: Multi-Channel, Low Power 24-Bit
Sensor AFE with True Continuous Background Calibration
1.0 General Description
The LMP90100/LMP90099/LMP90098/LMP90097 are highly
integrated, multi-channel, low power 24-bit Sensor AFEs. The
devices features a precision, 24-bit Sigma Delta Analog-to-
Digital Converter (ADC) with a low-noise programmable gain
amplifier and a fully differential high impedance analog input
multiplexer. A true continuous background calibration feature
allows calibration at all gains and output data rates without
interrupting the signal path. The background calibration fea-
ture essentially eliminates gain and offset errors across tem-
perature and time, providing measurement accuracy without
sacrificing speed and power consumption.
Another feature of the LMP90100/LMP90099/LMP90098/
LMP90097 is continuous background sensor diagnostics, al-
lowing the detection of open and short circuit conditions and
out-of-range signals, without requiring user intervention, re-
sulting in enhanced system reliability.
Two sets of independent external reference voltage pins allow
multiple ratiometric measurements. In addition, two matched
programmable current sources are available in the
LMP90100/LMP90098 to excite external sensors such as re-
sistive temperature detectors and bridge sensors. Further-
more, seven GPIO pins are provided for interfacing to external
LEDs and switches to simplify control across an isolation bar-
rier.
Collectively, these features make the LMP90100/LMP90099/
LMP90098/LMP90097 complete analog front-ends for low
power, precision sensor applications such as temperature,
pressure, strain gauge, and industrial process control. The
LMP90100/LMP90099/LMP90098/LMP90097 are guaran-
teed over the extended temperature range of -40°C to +125°
C and are available in a 28-pin TSSOP package.
2.0 Features
■
24-Bit Low Power Sigma Delta ADC
■
True Continuous Background Calibration at all gains
■
In-Place System Calibration using Expected Value
programming
■
Low-Noise programmable gain (1x - 128x)
■
Continuous background open/short and out of range
sensor diagnostics
■
8 output data rates (ODR) with single-cycle settling
■
2 matched excitation current sources from 100 µA to
1000 µA (LMP90100/LMP90098)
■
4-DIFF / 7-SE inputs (LMP90100/LMP90099)
■
2-DIFF / 4-SE inputs (LMP90098/LMP90097)
■
7 General Purpose Input/Output pins
■
Chopper-stabilized buffer for low offset
■
SPI 4/3-wire with CRC data link error detection
■
50 Hz to 60 Hz line rejection at ODR ≤13.42 SPS
■
Independent gain and ODR selection per channel
■
Supported by Webench Sensor AFE Designer
■
Automatic Channel Sequencer
3.0 Key Specifications
■ ENOB/NFR Up to 21.5/19 bits
■ Offset Error (typ) 8.4 nV
■ Gain Error (typ) 7 ppm
■ Total Noise < 10 µV-rms
■ Integral Non-Linearity (INL max) ±15 ppm of FSR
■ Output Data Rates (ODR) 1.6775 SPS - 214.65 SPS
■ Analog Voltage, VA +2.85V to +5.5V
■ Operating Temp Range -40°C to 125°C
■ Package 28-Pin TSSOP
4.0 Applications
■
Temperature and Pressure Transmitters
■
Strain Gauge Interface
■
Industrial Process Control
5.0 Typical Application
30139574
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation 301395 www.national.com
LMP90100/LMP90099/LMP90098/LMP90097 Sensor AFE System: Multi-Channel, Low Power 24-
Bit Sensor AFE with True Continuous Background Calibration
6.0 Block Diagram
30139575
FIGURE 1. Block Diagram
• True Continuous Background Calibration
The LMP90100/LMP90099/LMP90098/LMP90097 feature a
24 bit ΣΔ core with continuous background calibration to com-
pensate for gain and offset errors in the ADC, virtually elimi-
nating any drift with time and temperature. The calibration is
performed in the background without user or ADC input in-
terruption, making it unique in the industry and eliminating
down time associated with field calibration required with other
solutions. Having this continuous calibration improves perfor-
mance over the entire life span of the end product.
• Continuous Background Sensor Diagnostics
Sensor diagnostics are also performed in the background,
without interfering with signal path performance, allowing the
detection of sensor shorts, opens, and out-of-range signals,
which vastly improves system reliability. In addition, the fully
flexible input multiplexer described below allows any input pin
to be connected to any ADC input channel providing addi-
tional sensor path diagnostic capability.
• Flexible Input MUX Channels
The flexible input MUX allows interfacing to a wide range of
sensors such as thermocouples, RTDs, thermistors, and
bridge sensors. The LMP90100/LMP90099’s multiplexer sup-
ports 4 differential channels while the LMP90098/LMP90097
supports 2. Each effective input voltage that is digitized is VIN
= VINx – VINy, where x and y are any input. In addition, the
input multiplexer of the LMP90100/LMP90099 also supports
7 single-ended channels (LMP90098/LMP90097 supports 4),
where the common ground is any one of the inputs.
• Programmable Gain Amplifiers (FGA & PGA)
The LMP90100/LMP90099/LMP90098/LMP90097 contain
an internal 16x fixed gain amplifier (FGA) and a 1x, 2x, 4x, or
8x programmable gain amplifier (PGA). This allows accurate
gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x through
configuration of internal registers. Having an internal amplifier
eliminates the need for external amplifiers that are costly,
space consuming, and difficult to calibrate.
• Excitation Current Sources (IB1 & IB2) - LMP90100/
LMP90098
Two matched internal excitation currents, IB1 and IB2, can be
used for sourcing currents to a variety of sensors. The current
range is from 100 µA to 1000 µA in steps of 100 µA.
www.national.com 2
LMP90100/LMP90099/LMP90098/LMP90097
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Applications .................................................................................................................................... 1
5.0 Typical Application ........................................................................................................................... 1
6.0 Block Diagram ................................................................................................................................ 2
7.0 Ordering Information ........................................................................................................................ 5
8.0 Connection Diagram ........................................................................................................................ 5
9.0 Pin Descriptions .............................................................................................................................. 6
10.0 Absolute Maximum Ratings ............................................................................................................. 7
11.0 Operating Ratings .......................................................................................................................... 7
12.0 Electrical Characteristics ................................................................................................................ 7
13.0 Timing Diagrams ......................................................................................................................... 12
14.0 Specific Definitions ...................................................................................................................... 15
15.0 Typical Performance Characteristics .............................................................................................. 16
16.0 Functional Description .................................................................................................................. 22
16.1 SIGNAL PATH ..................................................................................................................... 22
16.1.1 Reference Input (VREF) .............................................................................................. 22
16.1.2 Flexible Input MUX (VIN) ............................................................................................. 22
16.1.3 Selectable Gains (FGA & PGA) .................................................................................... 23
16.1.4 Buffer (BUFF) ............................................................................................................ 23
16.1.5 Internal/External CLK Selection .................................................................................... 23
16.1.6 Programmable ODRs .................................................................................................. 23
16.1.7 Digital Filter ............................................................................................................... 24
16.1.8 GPIO (D0–D6) ........................................................................................................... 27
16.2 CALIBRATION ..................................................................................................................... 27
16.2.1 Background Calibration ............................................................................................... 27
16.2.2 System Calibration ...................................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................... 29
16.3 CHANNELS SCAN MODE ..................................................................................................... 29
16.4 SENSOR INTERFACE .......................................................................................................... 30
16.4.1 IB1 & IB2 - Excitation Currents ..................................................................................... 30
16.4.2 Burnout Currents ........................................................................................................ 30
16.4.3 Sensor Diagnostic Flags .............................................................................................. 30
16.5 SERIAL DIGITAL INTERFACE ............................................................................................... 32
16.5.1 Register Address (ADDR) ............................................................................................ 32
16.5.2 Register Read/Write Protocol ....................................................................................... 32
16.5.3 Streaming .................................................................................................................. 32
16.5.4 CSB - Chip Select Bar ................................................................................................. 33
16.5.5 SPI Reset .................................................................................................................. 33
16.5.6 DRDYB - Data Ready Bar ............................................................................................ 33
16.5.7 Data Only Read Transaction ........................................................................................ 36
16.5.8 Cyclic Redundancy Check (CRC) ................................................................................. 37
16.6 POWER MANAGEMENT ...................................................................................................... 38
16.7 RESET and RESTART .......................................................................................................... 38
17.0 Applications Information ............................................................................................................... 39
17.1 QUICK START ..................................................................................................................... 39
17.2 CONNECTING THE SUPPLIES ............................................................................................. 39
17.2.1 VA and VIO ............................................................................................................... 39
17.2.2 VREF ........................................................................................................................ 39
17.3 ADC_DOUT CALCULATION .................................................................................................. 39
17.4 REGISTER READ/WRITE EXAMPLES ................................................................................... 40
17.4.1 Writing to Register Examples ....................................................................................... 40
17.4.2 Reading from Register Example ................................................................................... 41
17.5 STREAMING EXAMPLES ..................................................................................................... 42
17.5.1 Normal Streaming Example ......................................................................................... 42
17.5.2 Controlled Streaming Example ..................................................................................... 43
17.6 EXAMPLE APPLICATIONS ................................................................................................... 45
17.6.1 3–Wire RTD ............................................................................................................... 45
17.6.2 Thermocouple and IC Analog Temperature .................................................................... 47
18.0 Registers .................................................................................................................................... 48
18.1 REGISTER MAP .................................................................................................................. 48
18.2 POWER AND RESET REGISTERS ........................................................................................ 49
18.3 ADC REGISTERS ................................................................................................................ 51
3 www.national.com
LMP90100/LMP90099/LMP90098/LMP90097
18.4 CHANNEL CONFIGURATION REGISTERS ............................................................................ 52
18.5 CALIBRATION REGISTERS .................................................................................................. 56
18.6 SENSOR DIAGNOSTIC REGISTERS ..................................................................................... 57
18.7 SPI REGISTERS .................................................................................................................. 58
18.8 GPIO REGISTERS ............................................................................................................... 60
19.0 Physical Dimensions .................................................................................................................... 61
List of Figures
FIGURE 1. Block Diagram ......................................................................................................................... 2
FIGURE 2. Timing Diagram ...................................................................................................................... 12
FIGURE 3. Simplified VIN Circuitry .............................................................................................................. 22
FIGURE 4. CLK Register Settings ............................................................................................................... 23
FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS .......................................................................... 24
FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS .............................................................................. 24
FIGURE 7. Digital Filter Response at 13.42 SPS ............................................................................................. 25
FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS .................................................................... 25
FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS ........................................................................ 26
FIGURE 10. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL ...................................................... 26
FIGURE 11. GPIO Register Settings ............................................................................................................ 27
FIGURE 12. Types of Calibration ................................................................................................................ 27
FIGURE 13. BgcalMode2 Register Settings ................................................................................................... 28
FIGURE 14. System Calibration Data-Flow Diagram ......................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................................................... 29
FIGURE 16. Burnout Currents .................................................................................................................... 30
FIGURE 17. Burnout Currents Injection for ScanMode3 ..................................................................................... 30
FIGURE 18. Sensor Diagnostic Flags Diagram ............................................................................................... 31
FIGURE 19. Register Read/Write Protocol ..................................................................................................... 32
FIGURE 20. DRDYB Behavior for a Complete ADC_DOUT Reading ..................................................................... 33
FIGURE 21. DRDYB Behavior for an ADC_DOUT not Read ............................................................................... 33
FIGURE 22. DRDYB Behavior for an Incomplete ADC_DOUT Reading .................................................................. 34
FIGURE 23. DrdybCase1 Connection Diagram ............................................................................................... 34
FIGURE 24. Timing Protocol for DrdybCase1 ................................................................................................. 35
FIGURE 25. Timing Protocol for DrdybCase2 ................................................................................................. 35
FIGURE 26. DrdybCase3 Connection Diagram ............................................................................................... 36
FIGURE 27. Timing Protocol for DrdybCase3 ................................................................................................. 36
FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT .................................................................................. 37
FIGURE 29. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds ...... 37
FIGURE 30. Active, Power-Down, Stand-by State Diagram ................................................................................ 38
FIGURE 31. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1). .................................................... 39
FIGURE 32. Register-Write Example 1 ......................................................................................................... 40
FIGURE 33. Register-Write Example 2 ......................................................................................................... 40
FIGURE 34. Register-Read Example ........................................................................................................... 41
FIGURE 35. Normal Streaming Example ....................................................................................................... 42
FIGURE 36. Setting up SPI_STREAMCN ...................................................................................................... 43
FIGURE 37. Controlled Streaming Example ................................................................................................... 44
FIGURE 38. Topology #1: 3-wire RTD Using 2 Current Sources ........................................................................... 45
FIGURE 39. Topology #2: 3-wire RTD Using 1 Current Source ............................................................................ 46
FIGURE 40. Thermocouple with CJC ........................................................................................................... 47
List of Tables
TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ................................. 11
TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V .................................................... 11
TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................. 11
TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................................... 11
TABLE 5. Data First Mode Transactions ........................................................................................................ 36
www.national.com 4
LMP90100/LMP90099/LMP90098/LMP90097
7.0 Ordering Information
Product Channel Configuration Current Sources
LMP90100 4 Differential / 7 Single-Ended Yes
LMP90099 4 Differential / 7 Single-Ended No
LMP90098 2 Differential / 4 Single-Ended Yes
LMP90097 2 Differential / 4 Single-Ended No
Order Code Temperature Range Description
LMP90100MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90100MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90100MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
LMP90099MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90099MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90099MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
LMP90098MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90098MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90098MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
LMP90097MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90097MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90097MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
8.0 Connection Diagram
30139576
See Pin Descriptions for specific information regarding options LMP90099, LMP90098, and LMP90097.
5 www.national.com
LMP90100/LMP90099/LMP90098/LMP90097
剩余61页未读,继续阅读
资源评论
brother23
- 粉丝: 1
- 资源: 7
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功