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PPC405-S Embedded Processor Core
User’s Manual
Version 1.0
July 19, 2007
Title Page
®
Copyright and Disclaimer
© Copyright International Business Machines Corporation 2005, 2007
All Rights Reserved
Printed in the United States of America July 2007
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or
both.
IBM PowerPC
IBM Logo PowerPC 400
ibm.com PowerPC Architecture
Other company, product, and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document
are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction
could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not
affect or change IBM® product specifications or warranties. Nothing in this document shall operate as an express or
implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this
document was obtained in specific environments, and is presented as an illustration. The results obtained in other oper
-
ating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be
liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Systems and Technology Group
2070 Route 52, Bldg. 330
Hopewell Junction, NY 12533-6351
The IBM home page can be found at ibm.com®
The IBM semiconductor solutions home page can be found at ibm.com/chips
title.fm.1.0
July 19, 2007
User’s Manual
PPC405-S Embedded Processor Core
ppc405STOC.fm.1.0
July 19, 2007
Contents
Page 3 of 547
List of Figures ............................................................................................................... 11
List of Tables ................................................................................................................. 15
About This Book ........................................................................................................... 19
1. Overview .................................................................................................................... 23
1.1 The PPC405-S as an Architectural Implementation ........................................................................ 24
1.2 Processor Core Organization .......................................................................................................... 25
1.2.1 Instruction and Data Cache Controllers ................................................................................. 25
1.2.1.1 Instruction Cache Unit .................................................................................................... 25
1.2.1.2 Data Cache Unit ............................................................................................................. 26
1.2.2 Memory Management Unit .................................................................................................... 26
1.2.3 Timer Facilities ...................................................................................................................... 27
1.2.4 Debug .................................................................................................................................... 28
1.2.4.1 Development Tool Support ............................................................................................. 28
1.2.4.2 Debug Modes ................................................................................................................. 28
1.2.5 Core Interfaces ...................................................................................................................... 28
1.2.5.1 Processor Local Bus ...................................................................................................... 29
1.2.5.2 Device Control Register Bus .......................................................................................... 29
1.2.5.3 Clock and Power Management ...................................................................................... 29
1.2.5.4 JTAG .............................................................................................................................. 29
1.2.5.5 Interrupts ....................................................................................................................... 29
1.2.5.6 Auxiliary Processor Unit ................................................................................................. 29
1.2.5.7 On-Chip Memory ............................................................................................................ 29
1.2.6 Data Types ............................................................................................................................ 29
1.2.7 Processor Core Register Set Summary ................................................................................ 30
1.2.7.1 General Purpose Registers ............................................................................................ 30
1.2.7.2 Special Purpose Registers ............................................................................................. 30
1.2.7.3 Machine State Register .................................................................................................. 30
1.2.7.4 Condition Register .......................................................................................................... 30
1.2.7.5 Device Control Registers ................................................................................................ 30
1.2.8 Addressing Modes ................................................................................................................. 31
1.2.9 Parity Detection ..................................................................................................................... 31
2. Programming Model ................................................................................................. 33
2.1 User and Privileged Programming Models ...................................................................................... 33
2.2 Memory Organization and Addressing ............................................................................................ 33
2.2.1 Storage Attributes .................................................................................................................. 33
2.3 Registers ......................................................................................................................................... 34
2.3.1 General Purpose Registers (R0-R31) ................................................................................... 36
2.3.2 Special Purpose Registers .................................................................................................... 36
2.3.2.1 Count Register (CTR) ..................................................................................................... 37
2.3.2.2 Link Register (LR) ......................................................................................................... 38
2.3.2.3 Fixed Point Exception Register (XER) ........................................................................... 38
2.3.2.4 Special Purpose Register General (SPRG0–SPRG7) ................................................... 40
Contents
User’s Manual
PPC405-S Embedded Processor Core
Contents
Page 4 of 547
ppc405STOC.fm.1.0
July 19, 2007
2.3.2.5 Processor Version Register (PVR) ................................................................................. 40
2.3.3 Condition Register (CR) ......................................................................................................... 41
2.3.3.1 CR Fields after Compare Instructions ............................................................................ 42
2.3.3.2 The CR0 Field ................................................................................................................ 42
2.3.4 The Time Base ....................................................................................................................... 43
2.3.5 Machine State Register (MSR) .............................................................................................. 43
2.3.6 Device Control Registers ....................................................................................................... 45
2.4 Data Types and Alignment .............................................................................................................. 45
2.4.1 Alignment for Storage Reference and Cache Control Instructions ........................................ 46
2.4.2 Alignment and Endian Operation ........................................................................................... 46
2.4.3 Summary of Instructions Causing Alignment Exceptions ...................................................... 47
2.5 Byte Ordering ................................................................................................................................. 47
2.5.1 Structure Mapping Examples ................................................................................................. 48
2.5.1.1 Big Endian Mapping ....................................................................................................... 48
2.5.1.2 Little Endian Mapping ..................................................................................................... 49
2.5.2 Support for Little Endian Byte Ordering ................................................................................. 49
2.5.3 Endian (E) Storage Attribute .................................................................................................. 49
2.5.3.1 Fetching Instructions from Little Endian Storage Regions .............................................. 49
2.5.3.2 Accessing Data in Little Endian Storage Regions .......................................................... 50
2.5.3.3 PowerPC Byte-Reverse Instructions .............................................................................. 51
2.6 Instruction Processing ..................................................................................................................... 52
2.7 Branch Processing .......................................................................................................................... 53
2.7.1 Unconditional Branch Target Addressing Options ................................................................. 53
2.7.2 Conditional Branch Target Addressing Options ..................................................................... 54
2.7.3 Conditional Branch Condition Register Testing ..................................................................... 54
2.7.4 BO Field on Conditional Branches ......................................................................................... 54
2.7.5 Branch Prediction ................................................................................................................... 55
2.8 Speculative Accesses ..................................................................................................................... 56
2.8.1 Speculative Accesses in the PPC405-S ................................................................................ 57
2.8.1.1 Prefetch Distance Down an Unresolved Branch Path .................................................... 57
2.8.1.2 Prefetch of Branches to the CTR and Branches to the LR ............................................. 57
2.8.2 Preventing Inappropriate Speculative Accesses .................................................................... 58
2.8.2.1 Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction ........................... 58
2.8.2.2 Fetching Past tw or twi Instructions ................................................................................ 59
2.8.2.3 Fetching Past an Unconditional Branch ......................................................................... 59
2.8.2.4 Suggested Locations of Memory-Mapped Hardware ..................................................... 59
2.8.3 Summary ................................................................................................................................ 60
2.9 Privileged Mode Operation .............................................................................................................. 60
2.9.1 MSR Bits and Exception Handling ......................................................................................... 60
2.9.2 Privileged Instructions ............................................................................................................ 61
2.9.3 Privileged SPRs ..................................................................................................................... 61
2.9.4 Privileged DCRs ..................................................................................................................... 62
2.10 Synchronization ............................................................................................................................. 62
2.10.1 Context Synchronization ...................................................................................................... 62
2.10.2 Execution Synchronization ................................................................................................... 64
2.10.3 Storage Synchronization ...................................................................................................... 65
2.11 Instruction Set ............................................................................................................................... 65
2.11.1 Instructions Specific to the IBM PowerPC Embedded Environment ................................... 66
2.11.2 Storage Reference Instructions ........................................................................................... 66
2.11.3 Arithmetic Instructions .......................................................................................................... 67
User’s Manual
PPC405-S Embedded Processor Core
ppc405STOC.fm.1.0
July 19, 2007
Contents
Page 5 of 547
2.11.4 Logical Instructions .............................................................................................................. 68
2.11.5 Compare Instructions .......................................................................................................... 68
2.11.6 Branch Instructions .............................................................................................................. 69
2.11.6.1 CR Logical Instructions ................................................................................................ 69
2.11.6.2 Rotate Instructions ....................................................................................................... 69
2.11.6.3 Shift Instructions ........................................................................................................... 70
2.11.6.4 Cache Management Instructions .................................................................................. 70
2.11.7 Interrupt Control Instructions ............................................................................................... 70
2.11.8 TLB Management Instructions ............................................................................................. 71
2.11.9 Processor Management Instructions ................................................................................... 71
2.11.10 Extended Mnemonics ........................................................................................................ 71
3. Initialization ............................................................................................................... 73
3.1 Processor State After Reset ............................................................................................................ 73
3.1.1 Machine State Register Contents after Reset ....................................................................... 74
3.1.2 Contents of Special Purpose Registers after Reset .............................................................. 74
3.2 PPC405-S Initial Processor Sequencing ......................................................................................... 75
3.3 Initialization Requirements .............................................................................................................. 75
3.4 Initialization Code Example ............................................................................................................. 76
4. Interrupts and Exceptions ........................................................................................ 79
4.1 Architectural Definitions and Behavior ............................................................................................ 79
4.2 Behavior of the PPC405-S Processor Core Implementation .......................................................... 80
4.3 Interrupt Handling Priorities ............................................................................................................. 81
4.4 Critical and Noncritical Interrupts .................................................................................................... 82
4.5 General Interrupt Handling Registers .............................................................................................. 84
4.5.1 Machine State Register (MSR) .............................................................................................. 84
4.5.2 Save/Restore Registers 0 and 1 (SRR0–SRR1) ................................................................... 86
4.5.3 Save/Restore Registers 2 and 3 (SRR2–SRR3) ................................................................... 87
4.5.4 Exception Vector Prefix Register (EVPR) ............................................................................. 88
4.5.5 Exception Syndrome Register (ESR) .................................................................................... 88
4.5.6 Data Exception Address Register (DEAR) ............................................................................ 90
4.5.7 Machine Check Syndrome Register (MCSR) ........................................................................ 91
4.6 Critical Input Interrupts .................................................................................................................... 92
4.7 Machine Check Interrupts ............................................................................................................... 92
4.7.1 Instruction Machine Check Handling ..................................................................................... 93
4.7.2 Data Machine Check Handling .............................................................................................. 94
4.8 Data Storage Interrupt ..................................................................................................................... 94
4.9 Instruction Storage Interrupt ............................................................................................................ 95
4.10 External Interrupt ........................................................................................................................... 96
4.10.1 External Interrupt Handling .................................................................................................. 96
4.11 Alignment Interrupt ........................................................................................................................ 97
4.12 Program Interrupt .......................................................................................................................... 98
4.13 FPU Unavailable Interrupt ............................................................................................................. 99
4.14 System Call Interrupt ..................................................................................................................... 99
4.15 APU Unavailable Interrupt ........................................................................................................... 100
4.16 Programmable Interval Timer (PIT) Interrupt .............................................................................. 100
4.17 Fixed Interval Timer (FIT) Interrupt ............................................................................................. 101
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