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数字仿真器使用方法vcs手册
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数字仿真器使用方法vcs手册
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VCS
®
/VCSi™
User Guide
K-2015.09, September 2015
ii
Copyright Notice and Proprietary Information
© 2015 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is
the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or
copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,
transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Tradema
rks.aspx.
All other product or company names may be trademarks of their respective owners.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse
and is not responsible for such websites and their practices, including privacy practices, availability, and content.
Synopsys, Inc.
690 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
iii
Contents
1. Getting Started
Simulator Support with Technologies . . . . . . . . . . . . . . . . . . . . . 1-2
Setting Up the Simulator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
V
erifying Your System Configuration . . . . . . . . . . . . . . . . . . . 1-4
Obt
aining a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Setting Up Y
our Environment. . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Setting Up Y
our C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Using the Simulator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Basic Usage Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Default T
ime Unit and Time Precision . . . . . . . . . . . . . . . . . . . . . 1-9
Searchi
ng Identifiers in the Design Using UNIX Commands . . . 1
-9
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-
11
2. VCS Flow
Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Using vcs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Commonly Used Options
. . . . . . . . . . . . . . . . . . . . . . . . . 2-3
iv
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Commonly Used Runti
me Options. . . . . . . . . . . . . . . . . . . . . 2-10
3. Modeling Yo
ur Design
Avoiding Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Using and Setting a V
alue at the Same Time . . . . . . . . . . . .
3-2
Setting a Value Twice at the Same Time . . . . . . . . . . . . . . . . 3
-3
Flip-Flop Race Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Continuous Assignment Evaluation . . . . . . . . . . . . . . . . . . . . 3
-5
Counting Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
T
ime Zero Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Race Detection
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
The Dynamic Race Detection Tool. . . . . . . . . . . . . . . . . . . . .
3-8
Introduction to the Dynamic Race Detection Tool
. . . . . . 3-8
Enabling Race Detection . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
The Race Detection Report . . . . . . . . . . . . . . . . . . . . . . . 3-12
Post Processing the Report . . . . . . . . . . . . . . . . . . . . . . .
3-15
Debugging Simulation Mismatches
. . . . . . . . . . . . . . . . . 3-17
The St
atic Race Detection Tool
. . . . . . . . . . . . . . . . . . . . . . . 3-20
Optimizing Testbenches for Debugging. . . . . . . . . . . . . . . . . . . . 3-22
Conditional Compilation. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 3-23
Enabling Debugging Features At Runtime. . . . . . . . . . . . . . . 3-24
Combining the Te
chniques . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Creating Models That Simulate Faster . . . . . . . . . . . . . . . . . . . . 3-28
v
Unaccelerated Data Types, Primitives, and Statements . . . . 3-29
Inferring Faster Simulating Sequential Devices. . . . . . . . . . . 3-31
Modeling Faster always Blocks . . . . . . . . . . . . . . . . . . . . . . . 3-35
Using Veril
og 2001 Constructs. . . . . . . . . . . . . . . . . . . . . . . .
3-36
Case Statement Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
Precedence in Te
xt Macro Definitions . . . . . . . . . . . . . . . . . . . . . 3-38
Memory Size Limits
in the Simulator . . . . . . . . . . . . . . . . . . . . . . 3-39
Using Sp
arse Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
Obta
ining Scope Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
Scope Format Sp
ecifications . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
Returning Information About the Scope
. . . . . . . . . . . . . . . . . 3-45
Av
oiding Circular Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
Designing Wi
th $lsi_dumpports for Simulation and Test
. . . . . . . 3-49
Dealing With Unassigned Nets . . . . . . . . . . . . . . . . . . . . . . . 3-50
Code Va
lues at Time 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
Cross Module Forces and No Instance Instantiation . . . . . . .
3-51
Signal Value/Strength Codes . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
4. Compiling the De
sign
Compiling or Elaborating the Design in Debug Mode . . . . . . . . . 4
-1
Compiling or Elaborating the Design in Optimized Mode . . . . . . 4
-3
Optimizing Simulation Performance for Desired Debug Vi
sibility with the
-debug_access Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Use Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
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