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### Freescale i.mx515 Datasheet关键知识点解析 #### 一、概述 - **产品背景**：Freescale Semiconductor（飞思卡尔半导体）是全球领先的嵌入式处理解决方案供应商之一，其产品广泛应用于汽车电子、网络、工业自动化以及消费电子等领域。i.mx515作为其多媒体应用处理器系列的一员，代表了公司在高性能、低功耗多媒体处理领域的最新成果。 - **主要功能**：i.mx515处理器采用先进的ARM Cortex-A8核心架构，并进行了专门的电源效率优化设计，最高工作频率可达800MHz。该处理器支持高达200MHz的DDR2和移动DDR DRAM时钟速率，适用于多种多媒体应用场景，包括但不限于： - Netbooks/Web Tablets（上网本/平板电脑） - Nettops（互联网桌面设备） - Mobile Internet Devices (MID)（移动互联网设备） - Portable Media Players (PMP)（便携式媒体播放器） - Portable Navigation Devices (PND)（便携式导航设备） - High-end PDAs（高端个人数字助理） - Gaming Consoles（游戏机） - Automotive Navigation and Entertainment（车载导航与娱乐系统） #### 二、产品特性 - **处理器核心**：采用ARM Cortex-A8内核，支持NEON SIMD引擎和VFPv3浮点单元，提供了高性能的计算能力。 - **内存支持**：支持DDR2和移动DDR DRAM内存类型，最大支持1GB容量。 - **多媒体功能**：集成高清视频编解码器，支持H.264、VC-1、MPEG-4等多种格式的视频解码；配备专用音频处理单元，支持多种音频格式。 - **外设接口**：提供丰富的外设接口，包括USB OTG、SD/MMC、I2C、SPI等标准接口，以及专为无线通信模块设计的WEIM接口。 - **低功耗设计**：通过动态电压和频率调节技术，实现高效的电源管理。 #### 三、配置与引脚分配 - **IOMUX配置**：为了适应不同的启动媒介和外设需求，i.mx515支持灵活的IOMUX配置，包括NAND闪存、SD/MMC卡、I2C总线、eCSPI/CSPI接口、无线外部接口模块(WEIM)、UART串行端口及USB-OTG等。 - **NAND配置**：支持高速NAND闪存，可配置为8位或16位数据宽度。 - **SD/MMC配置**：支持高速SD/MMC卡读写操作。 - **I2C配置**：支持多个I2C总线接口，用于连接传感器或其他外设。 - **eCSPI/CSPI配置**：支持增强型串行外围接口，用于连接各种SPI兼容设备。 - **WEIM配置**：支持无线外部接口模块，用于扩展无线通信功能。 - **UART配置**：支持多个通用异步收发器接口。 - **USB-OTG配置**：支持USB On-The-Go功能，实现设备间的直接通信。 #### 四、电气特性 - **芯片级条件**：详细介绍了芯片在不同工作模式下的电气参数，如电源电压范围、电流消耗等。 - **供电要求**：规定了处理器在启动和关闭过程中的电源顺序及限制条件。 - **I/O直流参数**：列出了输入输出端口在不同状态下的电流和电压值。 - **输出缓冲阻抗特性**：描述了输出缓冲器的阻抗特性，对于设计稳定的信号链路至关重要。 - **I/O交流参数**：提供了关于输入输出端口交流特性的信息，包括信号上升下降时间等。 - **模块定时**：详细描述了处理器内部各模块之间的时序关系。 - **外部外围接口**：介绍了处理器支持的各种外部接口的电气特性。 #### 五、封装信息 - **封装尺寸**：i.mx515提供了两种封装选项，分别是13x13mm（间距0.5mm）和19x19mm（间距0.8mm）的塑料封装。 - **球栅阵列（BGA）布局**：提供了详细的球栅阵列布局图，方便用户进行PCB设计。 #### 六、版本历史 - **修订历史**：文档最后部分提供了历次更新的主要内容概览，有助于了解产品的迭代历程和技术改进情况。 i.mx515是一款高性能、低功耗的多媒体应用处理器，适用于多种消费电子和工业应用领域。通过对该处理器的深入理解，可以更好地发挥其优势，满足不同场景的需求。

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: IMX51CEC

Rev. 4, 08/2010

IMX51

Package Information

Plastic Package

Case 2058 13 x 13 mm, 0.5 mm pitch

Case 2017 19 x 19 mm, 0.8 mm pitch

Ordering Information

See Table 1 on page 3 for ordering information.

1 Introduction

The i.MX51 multimedia applications processors

represent Freescale Semiconductor’s latest addition to a

growing family of multimedia-focused products offering

high performance processing optimized for lowest

power consumption.

The i.MX51 processors feature Freescale’s advanced and

power-efficient implementation of the ARM Cortex

A8™ core, which operates at speeds as high as

800 MHz. Up to 200 MHz DDR2 and mobile DDR

DRAM clock rates are supported. These devices are

suitable for applications such as the following:

• Netbooks (web tablets)

• Nettops (internet desktop devices)

• Mobile internet devices (MID)

• Portable media players (PMP)

• Portable navigation devices (PND)

• High-end PDAs

• Gaming consoles

• Automotive navigation and entertainment (see

automotive data sheet, IMX51AEC)

i.MX51 Applications

Processors for Consumer and

Industrial Products

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3

1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1. Special Signal Considerations . . . . . . . . . . . . . . . 12

3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . 14

3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 15

3.3. I

C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 15

3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 16

3.5. Wireless External Interface Module (WEIM) . . . . 16

3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 16

3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 16

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17

4.2. Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4. Output Buffer Impedance Characteristics . . . . . . 31

4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 34

4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 70

5. Package Information and Contact Assignments . . . . . 150

5.1. 13 x 13 mm Package Information . . . . . . . . . . . . 150

5.2. 19 x 19 mm Package Information . . . . . . . . . . . . 169

5.3. 13 × 13 mm, 0.5 Pitch Ball Map . . . . . . . . . . . . . 187

5.4. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 192

6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4

2 Freescale Semiconductor

Introduction

Features include the following:

• Smart Speed Technology—The heart of the i.MX51 processors is a level of power management

throughout the device that enables the rich suite of multimedia features and peripherals to achieve

minimum system power consumption in both active and various low-power modes. Smart Speed

Technology enables the designer to deliver a feature-rich product that requires levels of power that

are far less than typical industry expectations.

• Applications Processor—The i.MX51 processors boost the capabilities of high-tier portable

applications by providing for the ever-increasing MIPS needs of operating systems and games.

Freescale’s Dynamic Voltage and Frequency Scaling (DVFS) allows the device run at much lower

voltage and frequency with sufficient MIPS for tasks such as audio decode resulting in significant

power reduction.

• Multimedia Powerhouse—The multimedia performance of the i.MX51 processors is boosted by

a multi-level cache system and further enhanced by a Multi-Standard Hardware Video Codec,

autonomous Image Processing Unit, SD and HD720p Triple Video (TV) Encoder with triple video

DAC, Neon (including Advanced SIMD, 32-bit Single-Precision floating point support and Vector

Floating Point co-processor), and a programmable smart DMA (SDMA) controller.

• Powerful Graphics Acceleration—Graphics is the key to mobile game navigation, web

browsing, and other applications. The i.MX51 processors provide two independent, integrated

Graphics Processing Units: OpenGL ES 2.0 3D graphics accelerator (27 Mtri/s, 166 Mpix/s) and

OpenVG 1.1 2D graphics accelerator (166 Mpix/s).

• Interface Flexibility—The i.MX51 processor interface supports connection to all popular types of

external memories: DDR2, Mobile DDR, NOR Flash, PSRAM, Cellular RAM, NAND Flash

(MLC and SLC), and OneNAND. Designers seeking to provide products that deliver a rich

multimedia experience find a full suite of on-chip peripherals: LCD controller and CMOS sensor

interface, High-Speed USB On-The-Go with PHY, and three High-Speed USB hosts, multiple

expansion card ports (High-Speed MMC/SDIO Host and others), 10/100 Ethernet controller, and

a variety of other popular interfaces (PATA, UART, I

C, I

S serial audio, and SIM card, among

others).

• Increased Security—Because the need for advanced security for mobile devices continues to

increase, the i.MX51 processors deliver hardware-enabled security features that enable secure

e-commerce, digital rights management (DRM), information encryption, secure boot, and secure

software downloads. For detailed information about the MX51 security features contact your

Freescale representative.

Features

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4

Freescale Semiconductor 5

2Features

The i.MX51 processor contains a large number of digital and analog modules that are described in Table 2.

Table 2. i.MX51 Digital and Analog Modules

Block

Mnemonic

Block Name Subsystem Brief Description

1-WIRE 1-Wire

Interface

Connectivity

Peripherals

1-Wire support provided for interfacing with an on-board EEPROM, and smart

battery interfaces, for example: Dallas DS2502.

ARM Cortex

A8™

ARM Cortex

A8™ Platform

ARM The ARM Cortex A8™ Core Platform consists of the ARM Cortex A8™

processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains

the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data

cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor

and Debug modules. It also has a NEON co-processor with SIMD media

processing architecture, register file with 32 × 64-bit general-purpose registers,

an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating

point execute pipeline (FADD, FMUL), load/store and permute pipeline and a

Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).

Audio

Subsystem

Audio

Subsystem

Multimedia

Peripherals

The elements of the audio subsystem are three Synchronous Serial Interfaces

(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).

See the specific interface listings in this table.

AUDMUX Digital Audio

Mux

Multimedia

Peripherals

The AUDMUX is a programmable interconnect for voice, audio, and

synchronous data routing between host serial interfaces (for example, SSI1,

SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The

AUDMUX has seven ports (three internal and four external) with identical

functionality and programming models. A desired connectivity is achieved by

configuring two or more AUDMUX ports.

CCM

GPC

SRC

Clock Control

Module

Global Power

Controller

System Reset

Controller

Clocks,

Resets, and

Power

Control

These modules are responsible for clock and reset distribution in the system,

and also for system power management. The modules include three PLLs and

a Frequency Pre-Multiplier (FPM).

CSPI-1,

eCSPI-2

eCSPI-3

Configurable

SPI,

Enhanced

CSPI

Connectivity

Peripherals

Full-duplex enhanced Synchronous Serial Interface, with data rate up to

66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave

modes, four chip selects to support multiple peripherals.

CSU Central

Security Unit

Security The Central Security Unit (CSU) is responsible for setting comprehensive

security policy within the i.MX51 platform, and for sharing security information

between the various security modules. The Security Control Registers (SCR) of

the CSU are set during boot time by the High Assurance Boot (HAB) code and

are locked to prevent further writing.

Debug

System

Debug

System

Control

The Debug System provides real-time trace debug capability of both instructions

and data. It supports a trace protocol that is an integral part of the ARM Real

Time Debug solution (RealView). Real-time tracing is controlled by specifying a

set of triggering and filtering resources, which include address and data

comparators, cross-system triggers, counters, and sequencers.

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