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### CY7C6801A-56：深度解析EZ-USB FX2LP™ USB Microcontroller的关键特性 #### 概述与核心价值在现代电子设备与计算机系统的开发过程中，单片机作为核心组件之一，其性能与功能对整体系统的表现起着决定性作用。CY7C6801A-56，具体指的是EZ-USB FX2LP™ USB Microcontroller系列中的部分型号，是由Cypress Semiconductor Corporation设计与制造的一款高性能、低功耗的单片机。该系列单片机不仅整合了高速USB接口控制器，还内嵌了增强型8051微处理器，旨在为开发人员提供强大的数据处理能力与灵活的USB通信功能。 #### 高速USB外围控制器特性 - **USB 2.0兼容性**：该系列单片机已通过USB IF高速认证（TID #40460272），确保了其在USB 2.0环境下的稳定运行与高速数据传输能力。 - **单芯片集成设计**：集成了USB 2.0收发器、智能状态机引擎(SIE)以及增强型8051微处理器，减少了外部组件需求，简化了电路板布局与成本控制。 - **超低功耗**：ICCN（即芯片电流）在任何模式下均不超过85mA，特别适合于USB供电或电池供电的应用场景，如便携式设备。 #### 软件与内存支持 - **8051代码执行环境**：支持从内部RAM执行8051代码，该RAM可通过USB下载或从EEPROM加载，亦可连接外部存储设备（128针封装）进行程序扩展。 - **16KB内部代码/数据RAM**：为程序执行与数据处理提供了充足的内存空间，提高了运行效率与数据处理速度。 - **多类型端点配置**：具备四个可编程的BULK、INTERRUPT和ISOCHRONOUS端点，支持双缓冲、三缓冲及四缓冲选项，增强了数据传输的灵活性与稳定性。 - **额外的64字节端点**：提供了一个额外的可编程BULK/INTERRUPT端点，进一步丰富了数据交互方式。 #### 数据接口与扩展能力 - **8位或16位外部数据接口**：适应不同应用场景下的数据传输速率需求，增强了设备的适用范围。 - **智能媒体标准ECC生成**：支持错误校验与纠正机制，提升了数据传输的可靠性和安全性。 - **通用可编程接口(GPIF)**：允许直接连接到大多数并行接口，简化了与其他硬件设备的集成过程。 #### 增强型8051微处理器特性 - **多频操作模式**：支持48MHz、24MHz或12MHz CPU操作频率，满足不同应用对处理速度的需求。 - **高效指令周期**：每个指令周期只需四时钟周期，提高了代码执行效率。 - **丰富的通信与定时资源**：包含两个USART、三个计数器/定时器，以及扩展中断系统，支持复杂通信协议与实时控制任务。 - **双数据指针**：为数据访问与管理提供了更高级别的灵活性。 #### 其他关键特性 - **3.3V工作电压与5V容限输入**：兼容多种电源系统，增加了应用领域的广泛性。 - **矢量USB中断与GPIF/FIFO中断**：优化了中断处理流程，提高了系统的响应速度与处理效率。 - **分离数据缓冲区**：针对CONTROL传输的设置与数据部分提供了独立缓冲区，增强了数据传输的准确性和效率。 - **集成I2C控制器**：支持100KHz或400KHz工作频率，简化了与外部设备的通信连接。 - **四路集成FIFO**：内置逻辑与FIFO降低了系统成本，同时支持16位总线自动转换，便于与ASIC和DSP ICs等其他设备的接口。 - **温度等级选择**：适用于商业和工业温度范围，除了VFBGA封装外，所有封装类型均可选。 CY7C6801A-56作为EZ-USB FX2LP™ USB Microcontroller系列的一员，凭借其高度集成的设计、卓越的性能、广泛的适用性以及低功耗特性，在USB设备开发、嵌入式系统设计等领域展现出巨大的潜力与优势。对于追求高效、灵活且经济的解决方案的开发人员而言，该系列单片机无疑是理想的选择。

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

EZ-USB

FX2LP™ USB Microcontroller

High-Speed USB Peripheral Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-08032 Rev. *V Revised February 7, 2012

EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller

Features

■ USB 2.0 USB IF high speed certified (TID # 40460272)

■ Single chip integrated USB 2.0 transceiver, smart SIE, and

enhanced 8051 microprocessor

■ Fit, form, and function compatible with the FX2

❐ Pin compatible

❐ Object code compatible

❐ Functionally compatible (FX2LP is a superset)

■ Ultra low power: I

No more than 85 mA in any mode

❐ Ideal for bus and battery powered applications

■ Software: 8051 code runs from:

❐ Internal RAM, which is downloaded through USB

❐ Internal RAM, which is loaded from EEPROM

❐ External memory device (128 pin package)

■ 16 KB of on-chip code/data RAM

■ Four programmable BULK, INTERRUPT, and

ISOCHRONOUS endpoints

❐ Buffering options: Double, triple, and quad

■ Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

■ 8-bit or 16-bit external data interface

■ Smart media standard ECC generation

■ GPIF (general programmable interface)

❐ Enables direct connection to most parallel interfaces

❐ Programmable waveform descriptors and configuration

registers to define waveforms

❐ Supports multiple ready (RDY) inputs and Control (CTL)

outputs

■ Integrated, industry standard enhanced 8051

❐ 48 MHz, 24 MHz, or 12 MHz CPU operation

❐ Four clocks per instruction cycle

❐ Two USARTs

❐ Three counter/timers

❐ Expanded interrupt system

❐ Two data pointers

■ 3.3 V operation with 5 V tolerant inputs

■ Vectored USB interrupts and GPIF/FIFO interrupts

■ Separate data buffers for the setup and data portions of a

CONTROL transfer

■ Integrated I

C controller, runs at 100 or 400 kHz

■ Four integrated FIFOs

❐ Integrated glue logic and FIFOs lower system cost

❐ Automatic conversion to and from 16-bit buses

❐ Master or slave operation

❐ Uses external clock or asynchronous strobes

❐ Easy interface to ASIC and DSP ICs

■ Available in commercial and industrial temperature grade

(all packages except VFBGA)

Features (CY7C68013A/14A only)

■ CY7C68014A: Ideal for Battery Powered Applications

❐ Suspend current: 100 A (typ)

■ CY7C68013A: Ideal for Non Battery Powered Applications

❐ Suspend current: 300 A (typ)

■ Available in Five Pb-free Packages with Up to 40 GPIOs

❐ 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin

QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin

VFBGA (24 GPIOs)

Features (CY7C68015A/16A only)

■ CY7C68016A: Ideal for Battery Powered Applications

❐ Suspend current: 100 A (typ)

■ CY7C68015A: Ideal for Non Battery Powered Applications

❐ Suspend current: 300 A (typ)

■ Available in Pb-free 56-pin QFN Package (26 GPIOs)

■ Two more GPIOs than CY7C68013A/14A enabling additional

features in same footprint

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *V Page 2 of 66

Cypress’s EZ-USB

FX2LP (CY7C68013A/14A) is a low

power version of the EZ-USB FX2(CY7C68013), which is a

highly integrated, low power USB 2.0 microcontroller. By

integrating the USB 2.0 transceiver, serial interface engine (SIE),

enhanced 8051 microcontroller, and a programmable peripheral

interface in a single chip,

Cypress has created a cost effective solution that provides

superior time-to-market advantages with low power to enable

bus powered applications.

The ingenious architecture of FX2LP results in data transfer

rates of over 53 Mbytes per second, the maximum allowable

USB 2.0 bandwidth, while still using a low cost 8051

microcontroller in a package as small as a 56 VFBGA (5 mm x 5

mm). Because it incorporates the USB 2.0 transceiver, the

FX2LP is more economical, providing a smaller footprint solution

than USB 2.0 SIE or external transceiver implementations. With

EZ-USB FX2LP, the Cypress Smart SIE handles most of the

USB 1.1 and 2.0 protocol in hardware, freeing the embedded

microcontroller for application specific functions and decreasing

development time to ensure USB compatibility.

The General Programmable Interface (GPIF) and Master/Slave

Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and

glueless interface to popular interfaces such as

ATA, UTOPIA,

EPP, PCMCIA, and most DSP/processors.

The FX2LP draws less current than the FX2 (CY7C68013), has

double the on-chip code/data RAM, and is fit, form and function

compatible with the 56, 100, and 128 pin FX2.

Five packages are defined for the family: 56 VFBGA, 56 SSOP,

56 QFN, 100 TQFP, and 128 TQFP.

Address (16)

x20

PLL

/0.5

/1.0

/2.0

8051 Core

12/24/48 MHz,

four clocks/cycle

VCC

1.5k

D+

D–

Address (16) / Data Bus (8)

FX2LP

GPIF

Smart

USB

1.1/2.0

Engine

USB

2.0

XCVR

16 KB

RAM

4 kB

FIFO

Integrated

full speed and

Additional I/Os (24)

ADDR (9)

CTL (6)

RDY (6)

8/16

Data (8)

24 MHz

Ext. XTAL

Enhanced USB core

Simplifies 8051 code

“Soft Configuration”

Easy firmware changes

FIFO and endpoint memory

(master or slave operation)

Up to 96 MBytes/s

burst rate

General

programmable I/F

to ASIC/DSP or bus

standards such as

ATAPI, EPP, etc.

Abundant I/O

including two USARTs

High performance micro

using standard tools

with lower-power options

Master

connected for

full speed

ECC

XCVR

high speed

Logic Block Diagram

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *V Page 3 of 66

Contents

Applications ......................................................................4

Functional Overview ........................................................4

USB Signaling Speed ..................................................4

8051 Microprocessor ...................................................4

C Bus ........................................................................4

Buses ..........................................................................4

USB Boot Methods ......................................................5

ReNumeration .............................................................5

Bus-Powered Applications ..........................................5

Interrupt System ..........................................................5

Reset and Wakeup ......................................................7

Program/Data RAM .....................................................8

Endpoint RAM ...........................................................11

External FIFO Interface .............................................12

GPIF .......................................................................... 13

ECC Generation

[7] ................................................................... 13

USB Uploads and Downloads ...................................13

Autopointer Access ...................................................13

C Controller .............................................................14

Compatible with Previous Generation EZ-USB FX2 . 14

CY7C68013A/14A and CY7C68015A/16A Differences 14

Pin Assignments ............................................................15

CY7C68013A/15A Pin Descriptions ..........................22

Absolute Maximum Ratings ..........................................37

Operating Conditions .....................................................37

Thermal Characteristics .................................................37

DC Characteristics .........................................................38

USB Transceiver .......................................................38

AC Electrical Characteristics ........................................39

USB Transceiver .......................................................39

Program Memory Read .............................................39

Data Memory Read ...................................................40

Data Memory Write ................................................... 41

PORTC Strobe Feature Timings ...............................42

GPIF Synchronous Signals ....................................... 43

Slave FIFO Synchronous Read ................................. 44

Slave FIFO Asynchronous Read ...............................45

Slave FIFO Synchronous Write .................................46

Slave FIFO Asynchronous Write ............................... 47

Slave FIFO Synchronous Packet End Strobe ...........47

Slave FIFO Asynchronous Packet End Strobe ......... 48

Slave FIFO Output Enable ........................................49

Slave FIFO Address to Flags/Data ............................ 49

Slave FIFO Synchronous Address ............................49

Slave FIFO Asynchronous Address ..........................50

Sequence Diagram ....................................................50

Ordering Information ......................................................55

Ordering Code Definitions .........................................55

Package Diagrams ..........................................................56

PCB Layout Recommendations

....................................61

Quad Flat Package No Leads (QFN) Package

Design Notes ................................................................... 62

Acronyms ........................................................................63

Document Conventions .................................................63

Units of Measure .......................................................63

Document History Page .................................................64

Sales, Solutions, and Legal Information ......................66

Worldwide Sales and Design Support ....................... 66

Products .................................................................... 66

PSoC Solutions .........................................................66

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *V Page 4 of 66

1. Applications

■ Portable video recorder

■ MPEG/TV conversion

■ DSL modems

■ ATA interface

■ Memory card readers

■ Legacy conversion devices

■ Cameras

■ Scanners

■ Wireless LAN

■ MP3 players

■ Networking

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB 2.0 applications. Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Visit

www.cypress.com for more information.

2. Functional Overview

2.1 USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB

Specification Revision 2.0, dated April 27, 2000:

■ Full speed, with a signaling bit rate of 12 Mbps

■ High speed, with a signaling bit rate of 480 Mbps

FX2LP does not support the low speed signaling mode of

1.5 Mbps.

2.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has

256 bytes of register RAM, an expanded interrupt system, three

timer/counters, and two USARTs.

2.2.1 8051 Clock Frequency

FX2LP has an on-chip oscillator circuit that uses an external

24 MHz (±100 ppm) crystal with the following characteristics:

■ Parallel resonant

■ Fundamental mode

■ 500 W drive level

■ 12 pF (5% tolerance) load capacitors

An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,

as required by the transceiver/PHY and internal counters divide

it down for use as the 8051 clock. The default 8051 clock

frequency is 12 MHz. The clock frequency of the 8051 can be

changed by the 8051 through the CPUCS register, dynamically.

The CLKOUT pin, which can be three-stated and inverted using

internal control bits, outputs the 50% duty cycle 8051 clock, at

the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

2.2.2 USARTs

FX2LP contains two standard 8051 USARTs, addressed through

Special Function Register (SFR) bits. The USART interface pins

are available on separate I/O pins, and are not multiplexed with

port pins.

UART0 and UART1 can operate using an internal clock at

230 KBaud with no more than 1% baud rate error. 230 KBaud

operation is achieved by an internally derived clock source that

generates overflow pulses at the appropriate time. The internal

clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and

12 MHz) such that it always presents the correct frequency for

230 KBaud operation.

[1]

2.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast

access to critical FX2LP functions. These SFR additions are

shown in Table 1 on page 5. Bold type indicates non standard,

enhanced 8051 registers. The two SFR rows that end with “0”

and “8” contain bit addressable registers. The four I/O ports A to

D use the SFR addresses used in the standard 8051 for ports 0

to 3, which are not implemented in FX2LP. Because of the faster

and more efficient SFR addressing, the FX2LP I/O ports are not

addressable in external RAM space (using the MOVX

instruction).

2.3 I

C Bus

FX2LP supports the I

C bus as a master only at 100/400 KHz.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3V, even if no I

device is connected.

2.4 Buses

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,

multiplexed on I/O ports B and D. 128-pin package: adds 16-bit

output-only 8051 address bus, 8-bit bidirectional data bus.

Figure 2-1. Crystal Configuration

12 pf

24 MHz

20 × PLL

12 pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

Note

1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *V Page 5 of 66

2.5 USB Boot Methods

During the power up sequence, internal logic checks the I

C port

for the connection of an EEPROM whose first byte is either 0xC0

or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM

in place of the internally stored values (0xC0), or it boot-loads the

EEPROM contents into internal RAM (0xC2). If no EEPROM is

detected, FX2LP enumerates using internally stored descriptors.

The default ID values for FX2LP are VID/PID/DID (0x04B4,

0x8613, 0xAxxx where xxx = Chip revision).

[2]

2.6 ReNumeration

Because the FX2LP’s configuration is soft, one chip can take on

the identities of multiple distinct USB devices.

When first plugged into USB, the FX2LP enumerates

automatically and downloads firmware and USB descriptor

tables over the USB cable. Next, the FX2LP enumerates again,

this time as a device defined by the downloaded information.

This patented two step process called ReNumeration happens

instantly when the device is plugged in, without a hint that the

initial download step has occurred.

Two control bits in the USBCS (USB Control and Status) register,

control the ReNumeration process: DISCON and RENUM. To

simulate a USB disconnect, the firmware sets DISCON to 1. To

reconnect, the firmware clears DISCON to 0.

Before reconnecting, the firmware sets or clears the RENUM bit

to indicate whether the firmware or the Default USB Device

handles device requests over endpoint zero: if RENUM = 0, the

Default USB Device handles device requests; if RENUM = 1, the

firmware services the requests.

2.7 Bus-Powered Applications

The FX2LP fully supports bus powered designs by enumerating

with less than 100 mA as required by the USB 2.0 specification.

2.8 Interrupt System

2.8.1 INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4.

There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)

vectors. See EZ-USB Technical Reference Manual (TRM) for

more details.

2.8.2 USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that is required to identify the

individual USB interrupt source, the FX2LP provides a second

level of interrupt vectoring, called Autovectoring. When a USB

interrupt is asserted, the FX2LP pushes the program counter to

its stack, and then jumps to the address 0x0043 where it expects

to find a “jump” instruction to the USB Interrupt service routine.

Table 1. Special Function Registers

x 8x 9x Ax Bx Cx Dx Ex Fx

0 IOA IOB IOC IOD SCON1 PSW ACC B

1SP EXIF INT2CLR IOE SBUF1 – – –

2DPL0 MPAGE

INT4CLR OEA ––––

3DPH0 – – OEB ––––

4 DPL1 –– OEC ––––

5 DPH1 –– OED ––––

6 DPS –– OEE ––––

7PCON – – – – –––

8 TCON SCON0 IE IP T2CON EICON EIE EIP

9 TMOD SBUF0 – – – – – –

ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L – – –

BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H – – –

CTH0reserved EP68FIFOFLGS TL2 – – –

DTH1AUTOPTRH2 – GPIFSGLDATH TH2 – – –

E CKCON AUTOPTRL2 – GPIFSGLDATLX ––––

F–reserved AUTOPTRSET-UP GPIFSGLDATLNOX ––––

Table 2. Default ID Values for FX2LP

Default VID/PID/DID

Vendor ID 0x04B4 Cypress Semiconductor

Product ID 0x8613 EZ-USB FX2LP

Device release 0xAnnn Depends on chip revision

(nnn = chip revision where first

silicon = 001)

Note

2. The I

C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

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2015-04-23

资源很棒，算是比较全的了

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