指示灯cpld

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:31:21 06/20/2013 
// Design Name: 
// Module Name:    zhishideng 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module pilot_light(clk, key, led);
input clk, key;
output reg[2:0]led;
wire [1:0]div_3q;
wire [1:0]div_4q;
wire f1hz;
Div3 zzz(key,div_3q);
Div4 yyy(f1hz,div_4q);
Gen_1hz ppp(clk, f1hz);