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PCI Express® Base Specification Revision 6.0.1

PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and

assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to

update the information contained herein.

This PCI Specification is provided “as is” without any warranties of any kind, including any warranty of merchantability,

non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal,

specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of

information in this specification. This document itself may not be modified in any way, including by removing the

property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.

All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

Base 6.0.1 (Base 6.0 plus Errata as of 2022-08-29)

29 August 2022

1. Introduction..................................................................................................................................................................... 109

1.1 An Evolving I/O Interconnect .......................................................................................................................................... 109

1.2 PCI Express Link............................................................................................................................................................... 110

1.3 PCI Express Fabric Topology........................................................................................................................................... 111

1.3.1 Root Complex.......................................................................................................................................................... 112

1.3.2 Endpoints ................................................................................................................................................................ 113

1.3.2.1 Legacy Endpoint Rules.................................................................................................................................... 113

1.3.2.2 PCI Express Endpoint Rules ............................................................................................................................ 114

1.3.2.3 Root Complex Integrated Endpoint Rules...................................................................................................... 114

1.3.3 Switch ...................................................................................................................................................................... 115

1.3.4 Root Complex Event Collector................................................................................................................................ 116

1.3.5 PCI Express to PCI/PCI-X Bridge.............................................................................................................................. 116

1.4 Hardware/Soware Model for Discovery, Configuration and Operation...................................................................... 116

1.5 PCI Express Layering Overview....................................................................................................................................... 117

1.5.1 Transaction Layer.................................................................................................................................................... 118

1.5.2 Data Link Layer........................................................................................................................................................ 118

1.5.3 Physical Layer.......................................................................................................................................................... 118

1.5.4 Layer Functions and Services................................................................................................................................. 119

1.5.4.1 Transaction Layer Services............................................................................................................................. 119

1.5.4.2 Data Link Layer Services ................................................................................................................................. 120

1.5.4.3 Physical Layer Services................................................................................................................................... 120

1.5.4.4 Inter-Layer Interfaces...................................................................................................................................... 121

1.5.4.4.1 Transaction/Data Link Interface ............................................................................................................. 121

1.5.4.4.2 Data Link/Physical Interface................................................................................................................... 121

2. Transaction Layer Specification ..................................................................................................................................... 123

2.1 Transaction Layer Overview ........................................................................................................................................... 123

2.1.1 Address Spaces, Transaction Types, and Usage .................................................................................................... 123

2.1.1.1 Memory Transactions...................................................................................................................................... 124

2.1.1.2 I/O Transactions .............................................................................................................................................. 124

2.1.1.3 Configuration Transactions ............................................................................................................................ 124

2.1.1.4 Message Transactions ..................................................................................................................................... 125

2.1.2 Packet Format Overview......................................................................................................................................... 125

2.2 Transaction Layer Protocol - Packet Definition.............................................................................................................. 127

2.2.1 Common Packet Header Fields .............................................................................................................................. 127

2.2.1.1 Common Packet Header Fields for Non-Flit Mode ........................................................................................ 127

2.2.1.2 Common Packet Header Fields for Flit Mode................................................................................................. 130

2.2.2 TLPs with Data Payloads - Rules............................................................................................................................. 150

2.2.3 TLP Digest Rules - Non-Flit Mode Only................................................................................................................... 153

2.2.4 Routing and Addressing Rules................................................................................................................................ 154

2.2.4.1 Address-Based Routing Rules......................................................................................................................... 154

2.2.4.2 ID Based Routing Rules................................................................................................................................... 156

2.2.5 First/Last DW Byte Enables Rules ........................................................................................................................... 158

2.2.5.1 Byte Enable Rules for Non-Flit Mode.............................................................................................................. 159

2.2.5.2 Byte Enable Rules for Flit Mode...................................................................................................................... 162

2.2.6 Transaction Descriptor............................................................................................................................................ 162

2.2.6.1 Overview.......................................................................................................................................................... 162

Table of Contents

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2.2.6.2 Transaction Descriptor - Transaction ID Field................................................................................................ 162

2.2.6.3 Transaction Descriptor - Attributes Field ....................................................................................................... 169

2.2.6.4 Relaxed Ordering and ID-Based Ordering Attributes..................................................................................... 170

2.2.6.5 No Snoop Attribute ......................................................................................................................................... 170

2.2.6.6 Transaction Descriptor - Traic Class Field.................................................................................................... 171

2.2.7 Memory, I/O, and Configuration Request Rules..................................................................................................... 171

2.2.7.1 Non-Flit Mode.................................................................................................................................................. 171

2.2.7.1.1 TPH Rules ................................................................................................................................................ 175

2.2.7.2 Flit Mode .......................................................................................................................................................... 178

2.2.8 Message Request Rules........................................................................................................................................... 180

2.2.8.1 INTx Interrupt Signaling - Rules...................................................................................................................... 182

2.2.8.2 Power Management Messages ....................................................................................................................... 186

2.2.8.3 Error Signaling Messages................................................................................................................................ 187

2.2.8.4 Locked Transactions Support......................................................................................................................... 188

2.2.8.5 Slot Power Limit Support................................................................................................................................ 189

2.2.8.6 Vendor_Defined Messages.............................................................................................................................. 190

2.2.8.6.1 PCI-SIG Defined VDMs ............................................................................................................................. 192

2.2.8.6.2 Device Readiness Status (DRS) Message ................................................................................................ 192

2.2.8.6.3 Function Readiness Status Message (FRS Message).............................................................................. 194

2.2.8.6.4 Hierarchy ID Message.............................................................................................................................. 196

2.2.8.7 Ignored Messages............................................................................................................................................ 197

2.2.8.8 Latency Tolerance Reporting (LTR) Message.................................................................................................. 198

2.2.8.9 Optimized Buer Flush/Fill (OBFF) Message.................................................................................................. 199

2.2.8.10 Precision Time Measurement (PTM) Messages.............................................................................................. 200

2.2.8.11 Integrity and Data Encryption (IDE) Messages............................................................................................... 203

2.2.9 Completion Rules.................................................................................................................................................... 206

2.2.9.1 Completion Rules for Non-Flit Mode.............................................................................................................. 207

2.2.9.2 Completion Rules for Flit Mode...................................................................................................................... 209

2.2.10 TLP Prefix Rules....................................................................................................................................................... 210

2.2.10.1 TLP Prefix General Rules - Non-Flit Mode ...................................................................................................... 210

2.2.10.2 Local TLP Prefix Processing ............................................................................................................................ 211

2.2.10.2.1 Vendor Defined Local TLP Prefix ............................................................................................................ 211

2.2.10.3 Flit Mode Local TLP Prefix............................................................................................................................... 211

2.2.10.4 End-End TLP Prefix Processing - Non-Flit Mode ............................................................................................ 212

2.2.10.4.1 Vendor Defined End-End TLP Prefix....................................................................................................... 214

2.2.10.4.2 Root Ports with End-End TLP Prefix Supported .................................................................................... 214

2.2.11 OHC-E Rules - Flit Mode .......................................................................................................................................... 214

2.3 Handling of Received TLPs ............................................................................................................................................. 215

2.3.1 Request Handling Rules.......................................................................................................................................... 219

2.3.1.1 Data Return for Read Requests....................................................................................................................... 225

2.3.2 Completion Handling Rules.................................................................................................................................... 230

2.4 Transaction Ordering ...................................................................................................................................................... 233

2.4.1 Transaction Ordering Rules .................................................................................................................................... 233

2.4.2 Update Ordering and Granularity Observed by a Read Transaction .................................................................... 239

2.4.3 Update Ordering and Granularity Provided by a Write Transaction..................................................................... 240

2.5 Virtual Channel (VC) Mechanism .................................................................................................................................... 240

2.5.1 Virtual Channel Identification (VC ID)..................................................................................................................... 243

2.5.2 TC to VC Mapping .................................................................................................................................................... 244

2.5.3 VC and TC Rules....................................................................................................................................................... 245

2.6 Ordering and Receive Buer Flow Control..................................................................................................................... 246

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2.6.1 Flow Control (FC) Rules........................................................................................................................................... 247

2.6.1.1 FC Information Tracked by Transmitter ......................................................................................................... 254

2.6.1.2 FC Information Tracked by Receiver............................................................................................................... 259

2.7 End-to-End Data Integrity ............................................................................................................................................... 265

2.7.1 ECRC Rules............................................................................................................................................................... 265

2.7.2 Error Forwarding (Data Poisoning)......................................................................................................................... 270

2.7.2.1 Rules For Use of Data Poisoning..................................................................................................................... 271

2.8 Completion Timeout Mechanism................................................................................................................................... 272

2.9 Link Status Dependencies............................................................................................................................................... 273

2.9.1 Transaction Layer Behavior in DL_Down Status.................................................................................................... 273

2.9.2 Transaction Layer Behavior in DL_Up Status......................................................................................................... 274

2.9.3 Transaction Layer Behavior During Downstream Port Containment ................................................................... 275

3. Data Link Layer Specification ......................................................................................................................................... 277

3.1 Data Link Layer Overview ............................................................................................................................................... 277

3.2 Data Link Control and Management State Machine ...................................................................................................... 278

3.2.1 Data Link Control and Management State Machine Rules .................................................................................... 279

3.3 Data Link Feature Exchange............................................................................................................................................ 282

3.4 Flow Control Initialization Protocol ............................................................................................................................... 284

3.4.1 Flow Control Initialization State Machine Rules .................................................................................................... 284

3.4.2 Scaled Flow Control ................................................................................................................................................ 292

3.5 Data Link Layer Packets (DLLPs)..................................................................................................................................... 292

3.5.1 Data Link Layer Packet Rules.................................................................................................................................. 293

3.6 Data Integrity Mechanisms ............................................................................................................................................. 302

3.6.1 Introduction............................................................................................................................................................. 302

3.6.2 LCRC, Sequence Number, and Retry Management (TLP Transmitter).................................................................. 303

3.6.2.1 LCRC and Sequence Number Rules (TLP Transmitter).................................................................................. 303

3.6.2.2 Handling of Received DLLPs (Non-Flit Mode) ................................................................................................ 311

3.6.2.3 Handling of Received DLLPs (Flit Mode) ........................................................................................................ 312

3.6.3 LCRC and Sequence Number (TLP Receiver) (Non-Flit Mode) .............................................................................. 313

3.6.3.1 LCRC and Sequence Number Rules (TLP Receiver) ....................................................................................... 313

4. Physical Layer Logical Block........................................................................................................................................... 319

4.1 Introduction..................................................................................................................................................................... 319

4.2 Logical Sub-block............................................................................................................................................................ 319

4.2.1 8b/10b Encoding for 2.5 GT/s and 5.0 GT/s Data Rates .......................................................................................... 321

4.2.1.1 Symbol Encoding ............................................................................................................................................ 321

4.2.1.1.1 Serialization and De-serialization of Data.............................................................................................. 322

4.2.1.1.2 Special Symbols for Framing and Link Management (K Codes) ........................................................... 323

4.2.1.1.3 8b/10b Decode Rules .............................................................................................................................. 324

4.2.1.2 Framing and Application of Symbols to Lanes .............................................................................................. 325

4.2.1.2.1 Framing and Application of Symbols to Lanes for TLPs and DLLPs in Non-Flit Mode......................... 325

4.2.1.3 Data Scrambling.............................................................................................................................................. 328

4.2.2 128b/130b Encoding for 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s Data Rates ................................................................ 329

4.2.2.1 Lane Level Encoding ....................................................................................................................................... 330

4.2.2.2 Ordered Set Blocks.......................................................................................................................................... 331

4.2.2.2.1 Block Alignment...................................................................................................................................... 331

4.2.2.3 Data Blocks...................................................................................................................................................... 332

4.2.2.3.1 Framing Tokens in Non-Flit-Mode .......................................................................................................... 332

4.2.2.3.2 Transmitter Framing Requirements in Non-Flit Mode........................................................................... 337

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

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