ads7862说明资源-CSDN文库

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### ADS7862知识点详解 #### 一、产品概述 **ADS7862**是BB公司推出的一款低功耗、12位分辨率、具备4通道的模拟数字转换器（AD转换器）。该器件特别设计用于需要高速度与高精度的信号采集应用场合。 #### 二、主要特性 1. **双通道500kHz采样率**：ADS7862支持每通道高达500kHz的采样频率。 2. **12位分辨率**：提供高精度的数据转换能力。 3. **2+2通道同时采样**：可以对四个完全差分输入通道进行分组，并实现两组之间的同步采样。 4. **全面差分输入**：输入信号为完全差分形式，这有助于在高噪声环境中提高共模抑制比。 5. **2微秒总吞吐量/通道**：快速完成转换过程，适用于需要快速响应的应用场景。 6. **无缺失码保证**：确保转换过程中不会出现跳码现象，提高了数据的可靠性。 7. **并行接口**：简化了与外部处理器的连接，降低了软件开销。 8. **1MHz有效采样率**：对于单个通道而言，最高可以达到1MHz的有效采样速度。 9. **低功耗设计**：工作时的功率消耗仅为40mW，适合于电池供电或对能耗有严格限制的应用场景。 #### 三、应用场景 1. **电机控制**：利用其高精度与快速响应的特点，适用于精密电机的实时控制。 2. **多轴定位系统**：能够同时处理多个轴的位置反馈信号，适用于需要高精度位置控制的工业自动化设备。 3. **三相电源控制**：适用于电力电子领域中的电源监控与管理，如变频器等。 #### 四、内部结构与工作原理 - **采样保持放大器**：输入端通过采样保持放大器，可将模拟信号稳定地保持一段时间，以便进行准确的A/D转换。 - **差分输入**：每个通道都具有差分输入，提高了信号的抗干扰能力。 - **逐次逼近寄存器（SAR）型AD转换器**：采用逐次逼近寄存器技术实现模数转换，具有速度快、精度高的特点。 - **并行数据输出**：转换后的数字数据通过并行接口输出，方便与处理器进行数据交换。 - **内部参考电压源**：内置一个2.5V的参考电压源，简化了电路设计。 #### 五、引脚说明 1. **REFIN (引脚1)**：参考电压输入端。 2. **REFOUT (引脚2)**：+2.5V参考电压输出端，当使用内部参考电压时应直接连接到REFIN引脚。 3. **AGND (引脚3)**：模拟地。 4. **+VA (引脚4)**：模拟电源供应端，一般接+5V DC，建议直接连接至数字电源引脚，并进行适当的去耦处理。 #### 六、注意事项 - 在使用内部参考电压时，必须确保REFIN与REFOUT之间正确连接。 - 对于高速应用，需要考虑信号完整性问题，例如适当布局、去耦电容的选择等。 - 在实际应用中，根据具体需求选择合适的外部组件进行信号调理。 - 使用时注意操作温度范围为-40°C至+85°C。 ### 结论 ADS7862是一款性能优异、功能丰富的AD转换器，尤其适用于需要高速度与高精度信号采集的场合。其全面差分输入、高速转换能力和低功耗设计等特点使其成为电机控制、多轴定位系统及三相电源控制等领域中的理想选择。

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Dual 500kHz, 12-Bit, 2 + 2 Channel

Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 4 INPUT CHANNELS

● FULLY DIFFERENTIAL INPUTS

● 2µs TOTAL THROUGHPUT PER CHANNEL

● GUARANTEED NO MISSING CODES

● PARALLEL INTERFACE

● 1MHz EFFECTIVE SAMPLING RATE

● LOW POWER: 40mW

APPLICATIONS

● MOTOR CONTROL

● MULTI-AXIS POSITIONING SYSTEMS

● 3-PHASE POWER CONTROL

DESCRIPTION

The ADS7862 is a dual 12-bit, 500kHz analog-to-digital

converter (A/D) with 4 fully differential input channels grouped

into two pairs for high speed simultaneous signal acquisition.

Inputs to the sample-and-hold amplifiers are fully differential

and are maintained differential to the input of the A/D con-

verter. This provides excellent common-mode rejection of

80dB at 50kHz, which is important in high noise environ-

ments.

The ADS7862 offers parallel interface and control inputs to

minimize software overhead. The output data for each channel

is available as a 12-bit word. The ADS7862 is offered in an

TQFP-32 package and is fully specified over the –40°C to

+85°C operating range.

ADS7862

SAR

Interface

Conversion

and

Control

Output

Registers

COMP

CONVST

BUSY

Data Output

CLOCK

CDAC

Internal

2.5V

Reference

S/H

Amp

S/H

Amp

CH A0–

CH A0+

REF

CH A1–

CH A1+

SAR

COMP

CDAC

MUX

CH B0–

CH B0+

CH B1–

CH B1+

REF

OUT

ADS7862

SBAS101B – JANUARY 1998 – REVISED AUGUST 2005

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

ADS7862

SBAS101B

www.ti.com

PIN NAME DESCRIPTION

1REF

Reference Input

2 REF

OUT

+2.5V Reference Output. Connect directly to REF

(pin 1) when using internal reference.

3 AGND Analog Ground

4+V

Analog Power Supply, +5VDC. Connect directly to

digital power supply (pin 24). Decouple to analog

ground with a 0.1µF ceramic capacitor and a 10µF

tantalum capacitor.

5 DB11 Data Bit 11, MSB

6 DB10 Data Bit 10

7 DB9 Data Bit 9

8 DB8 Data Bit 8

9 DB7 Data Bit 7

10 DB6 Data Bit 6

11 DB5 Data Bit 5

12 DB4 Data Bit 4

13 DB3 Data Bit 3

14 DB2 Data Bit 2

15 DB1 Data Bit 1

16 DB0 Data Bit 0, LSB

17 BUSY HIGH when a conversion is in progress.

18 CONVST Convert Start

19 CLOCK An external CMOS-compatible clock can be applied to

the CLOCK input to synchronize the conversion pro-

cess to an external source. The CLOCK pin controls

the sampling rate by the equation: CLOCK 16 • f

SAMPLE

20 CS Chip Select

21 RD Synchronization pulse for the parallel output. During a

Read operation, the first falling edge selects the A

A0, then controls whether input 0 or input 1 is read.

22 A0 On the falling edge of Convert Start, when A0 is LOW

Channel A0 and Channel B0 are converted and when

it is HIGH, Channel A1 and Channel B1 are converted.

During a Read operation, the first falling edge selects

the A register and the second edge selects the B of RD

read.

23 DGND Digital Ground. Connect directly to analog ground (pin 3).

24 +V

Digital Power Supply, +5VDC

25 CH B1+ Non-Inverting Input Channel B1

26 CH B1– Inverting Input Channel B1

27 CH B0+ Non-Inverting Input Channel B0

28 CH B0– Inverting Input Channel B0

29 CH A1– Inverting Input Channel A1

30 CH A1+ Non-Inverting Input Channel A1

31 CH A0– Inverting Input Channel A0

32 CH A0+ Non-Inverting Input Channel A0

PIN CONFIGURATION

Top View

PIN DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGS

Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+V

+ 0.3V)

REF

............................. –0.3V to (+V

+ 0.3V)

Digital Inputs to DGND .......................................... –0.3V to (+V

+ 0.3V)

Ground Voltage Differences: AGND, DGND ................................... ±0.3V

to AGND ......................... –0.3V to +6V

Power Dissipation .......................................................................... 325mW

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and

installation procedures can cause damage.

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes

could cause the device not to meet its published specifications.

REF

OUT

AGND

DB11

DB10

DB9

DB8

DGND

CLOCK

CONVST

BUSY

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

9 10111213141516

CH A0+

CH A0–

CH A1+

CH A1–

CH B0–

CH B0+

CH B1–

CH B1+

32 31 30 29 28

ADS7862

27 26 25

ORDERING INFORMATION

(1)

MAXIMUM MAXIMUM

RELATIVE GAIN SPECIFICATION

ACCURACY ERROR PACKAGE TEMPERATURE ORDERING TRANSPORT

PRODUCT (LSB) (%) PACKAGE DESIGNATOR RANGE NUMBER MEDIA, QUANTITY

ADS7862Y ±2 ±0.75 TQFP-32 PBS –40°C to +85°C ADS7862Y/250 Tape and Reel, 250

ADS7862Y

"" " " "ADS7862Y/2K5 Tape and Reel, 2500

ADS7862YB ±1 ±0.5 TQFP-32 PBS –40°C to +85°C ADS7862YB/250 Tape and Reel, 250

ADS7862YB

"" " " "ADS7862YB/2K5 Tape and Reel, 2500

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.

ADS7862

SBAS101B

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications T

MIN

to T

MAX

, +V

= +V

= +5V, V

REF

= internal +2.5V and f

CLK

= 8MHz, f

SAMPLE

= 500kHz, unless otherwise noted.

ADS7862Y ADS7862YB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 12 ✻ Bits

ANALOG INPUT

Input Voltage Range-Bipolar V

CENTER

= Internal V

REF

at 2.5V –V

REF

✻✻V

Absolute Input Range +IN –0.3 V

+ 0.3 V

–IN –0.3 V

+ 0.3 V

Input Capacitance 15 ✻ pF

Input Leakage Current CLK = GND ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 12 ✻ Bits

Integral Linearity ±0.75 ±2 ±0.5 ±1 LSB

Integral Linearity Match 0.5 1 ✻✻ LSB

Differential Linearity ±0.75 ±0.5 ±1 LSB

Bipolar Offset Error Referenced to REF

±0.75 ±3 ±0.5 ±2 LSB

Bipolar Offset Error Match 3 2 LSB

Positive Gain Error Referenced to REF

±0.15 ±0.75 ±0.1 ±0.5 % of FSR

Positive Gain Error Match 2 1 LSB

Negative Gain Error Referenced to REF

±0.15 ±0.75 ±0.1 ±0.5 % of FSR

Negative Gain Error Match 2 1 LSB

Common-Mode Rejection Ratio At DC 80 ✻ dB

= ±1.25V

at 50kHz 80 ✻ dB

Noise 120 ✻ µV

RMS

Power Supply Rejection Ratio ±0.5 ±2 ✻✻ LSB

SAMPLING DYNAMICS

Conversion Time per A/D 1.75 ✻ µs

Acquisition Time 0.25 ✻ µs

Throughput Rate 500 ✻ kHz

Aperture Delay 3.5 ✻ ns

Aperture Delay Matching 100 ✻ ps

Aperture Jitter 50 ✻ ps

Small-Signal Bandwidth 40 ✻ MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion V

= ±2.5V

at 100kHz 75 ✻ dB

SINAD V

= ±2.5V

at 100kHz 71 ✻ dB

Spurious Free Dynamic Range V

= ±2.5V

at 100kHz –78 ✻ dB

Channel-to-Channel Isolation V

= ±2.5V

at 100kHz –80 ✻ dB

VOLTAGE REFERENCE

Internal 2.475 2.5 2.525 ✻✻✻ V

Internal Drift ±25 ✻ ppm/°C

Internal Noise 50 ✻ µV

Internal Source Current 2 ✻ mA

Internal Load Rejection 0.005 ✻ mV/µA

Internal PSRR 65 ✻ dB

External Voltage Range 1.2 2.5 2.6 ✻✻✻ V

Input Current 0.05 1 ✻✻ µA

Input Capacitance 5 ✻ pF

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻

Logic Levels: V

= +5µA 3.0

+ 0.3

✻✻V

= +5µA –0.3 0.8 ✻✻V

= –500µA 3.5 ✻ V

= 500µA 0.4 ✻ V

External Clock 0.2 8 ✻✻MHz

Data Format Binary Two’s Complement ✻

POWER SUPPLY REQUIREMENTS

Power Supply Voltage, +V 4.75 5 5.25 ✻✻✻ V

Quiescent Current, +V

58 ✻✻ mA

Power Dissipation 25 40 ✻✻ mW

✻ Specifications same as ADS7862Y.

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