基于ad0820的vhdl控制器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adc0820 is
    Port ( d   : in  STD_LOGIC_VECTOR (7 downto 0);
        clk : in  STD_LOGIC;           
           int : in  STD_LOGIC;
  cs  : out  STD_LOGIC;
           wr  : out  STD_LOGIC;
           rd  : out STD_LOGIC;
           q   : out  STD_LOGIC_VECTOR (7 downto 0));
end adc0820;

architecture Behavioral of adc0820 is
TYPE states is(st0,st1,st2,st3,st4);
signal cur_state :states;
signal nex_state :states :=st0;
signal lock : std_logic;
signal dtmp : std_logic_vector(7 downto 0) :="00000000";
signal clktmp :std_logic :='1';
begin

  process(clk)