implementing pll recofiguration stratix
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© May 2009 Altera Corporation AN 367: Implementing PLL Reconfiguration in Stratix II Devices
AN-367-2.1
© May 2009
AN 367: Implementing PLL
Reconfiguration in Stratix II Devices
Introduction
Phase-locked loops (PLLs) use several divide counters and different
voltage-controlled oscillator (VCO) phase taps to perform frequency synthesis and
phase shifts. In Stratix
®
II enhanced and fast PLLs, you can reconfigure both the
counter settings and phaseshift the PLL output clock in real time. You can also change
the charge pump and loop filter components, which dynamically affects the PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phaseshift in real time, without reconfiguring the entire FPGA.
The ability to reconfigure the PLL in real time is useful in applications that might
operate at multiple frequencies. It is also useful in prototyping environments,
allowing you to sweep PLL output frequencies and adjust the output clock phase on
the fly. For instance, a system generating test patterns is required to generate and
transmit patterns at 50 or 100 MHz, depending on the device under test.
Reconfiguring the PLL components in real time allows you to switch between two
such output frequencies in a few microseconds. You can also use this feature to adjust
clock-to-out (t
CO
) delays in real time by changing output clock phase shift. This
approach eliminates the need to regenerate a configuration file with the new PLL
settings.
This application note discusses the following:
■ “PLL Reconfiguration Hardware Implementation” on page 2
■ “Reconfigurable Phase Shift” on page 8
■ “Charge Pump and Loop Filter” on page 10
■ “Bypassing PLL Counters” on page 13
■ “Implementing Reconfigurable PLLs in the Quartus II Software” on page 14
■ “PLL Configuration Scan Register Bit Map” on page 18
■ “Design Considerations” on page 22
■ “Phase Shift Stepping” on page 23
■ “Ports and Parameters” on page 25
■ “Reconfiguring the C0 Counter Using ALTPLL_RECONFIG” on page 29
■ “Design Examples” on page 31
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