DATA SHEET
( DOC No. HX8347
-
G(T)
-
DS )
HX8347-G(T)
240RGB x 320 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Preliminary version 01 October, 2009
For 思泉 Only
-P.2-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
October, 2009
1. General Description ............................................................................................................................... 12
2. Features................................................................................................................................................... 13
2.1 Display........................................................................................................................................... 13
2.2 Display Module .............................................................................................................................. 13
2.3 Display Control Interface ............................................................................................................... 13
2.4 Input power.................................................................................................................................... 14
2.5 Miscellaneous................................................................................................................................ 14
3. Block Diagram ........................................................................................................................................ 15
3.1 Block diagram................................................................................................................................ 15
3.2 Pin description ............................................................................................................................... 16
3.3 Pin assignment .............................................................................................................................. 19
3.4 PAD coordinates............................................................................................................................ 20
3.5 Bump arrangement........................................................................................................................ 26
3.6 Alignment mark.............................................................................................................................. 27
4. Interface................................................................................................................................................... 28
4.1 System interface circuit ................................................................................................................. 29
4.1.1 Parallel bus system interface................................................................................................ 30
4.1.2 MCU data color coding......................................................................................................... 32
4.1.3 Serial bus system interface .................................................................................................. 45
4.2 RGB Interface................................................................................................................................ 49
4.2.1 Color order on RGB interface............................................................................................... 53
4.2.2 RGB data color coding ......................................................................................................... 54
5. Function Description.............................................................................................................................. 57
5.1 Display data GRAM mapping ........................................................................................................ 57
5.2 Address Counter (AC) of GRAM ................................................................................................... 57
5.2.1 System interface to GRAM write direction............................................................................ 58
5.3 GRAM to display address mapping............................................................................................... 63
5.3.1 Normal display on or partial mode on, vertical scroll off....................................................... 65
5.3.2 Vertical scroll display mode .................................................................................................. 67
5.3.3 Updating order on display active area in RGB interface mode ............................................ 70
5.4 Tearing effect output line ............................................................................................................... 73
5.4.1 Tearing effect line modes...................................................................................................... 73
5.4.2 Tearing effect line timing....................................................................................................... 75
5.4.3 Example 1: MPU write is faster than panel read .................................................................. 76
5.4.4 Example 2: MPU write is slower than panel read................................................................. 77
5.5 Oscillator........................................................................................................................................ 78
5.6 Source driver ................................................................................................................................. 78
5.7 Gate driver..................................................................................................................................... 78
5.8 Scan mode setting......................................................................................................................... 79
5.9 LCD power generation circuit ........................................................................................................ 80
5.9.1 Power supply circuit.............................................................................................................. 80
5.9.2 LCD power generation scheme............................................................................................ 82
5.10 Gamma characteristic correction function ..................................................................................... 83
5.10.1 Gamma characteristic correction function ............................................................................ 84
5.10.2 Gray voltage generator for digital gamma correctionearing effect line modes................... 104
5.11 Power on/off sequence................................................................................................................ 105
5.12 Input/output pin state ................................................................................................................... 109
5.12.1 Output pins ......................................................................................................................... 109
5.12.2 Input pins ............................................................................................................................ 109
5.13 OTP Programing...........................................................................................................................110
5.13.1 OTP table.............................................................................................................................110
5.13.2 OTP programming flow........................................................................................................111
5.14 Content Adaptive Brightness Control (CABC) function ................................................................113
5.14.1 Module architectures ...........................................................................................................114
5.14.2 Brightness control block ......................................................................................................115
5.14.3 Minimum brightness setting of CABC function....................................................................116
HX8347-G(T)
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
October, 2009
For 思泉 Only
-P.3-
Himax Confidential
October, 2009
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
5.14.4 Display dimming ..................................................................................................................116
6. Command.............................................................................................................................................. 117
6.1 Command set ...............................................................................................................................118
6.2 Index register............................................................................................................................... 123
6.3 Himax ID register (PAGE0 - R00h).............................................................................................. 123
6.4 Display mode control register (PAGE0 -01h) .............................................................................. 123
6.5 Column address start register (PAGE0 -02~03h)........................................................................ 124
6.6 Column address end register (PAGE0 -04~05h)......................................................................... 125
6.7 Row address start register (PAGE0 -06~07h) ............................................................................. 125
6.8 Row address end register (PAGE0 -08~09h).............................................................................. 125
6.9 Partial area start row register (PAGE0 -0A~0Bh)........................................................................ 126
6.10 Partial area end row register (PAGE0 -0C~0Dh)......................................................................... 126
6.11 Vertical scroll top fixed area register (PAGE0 -0E~0Fh) ............................................................. 128
6.12 Vertical scroll height area register (PAGE0 -10~11h).................................................................. 128
6.13 Vertical scroll button fixed area register (PAGE0 -12~13h)......................................................... 128
6.14 Vertical scroll start address register (PAGE0 -14~15h)............................................................... 130
6.15 Memory access control register (PAGE0 -16h) ........................................................................... 131
6.16 COLMOD control register (PAGE0 -17h)..................................................................................... 132
6.17 OSC control register (PAGE0 -18h & R19h) ............................................................................... 133
6.18 Power control 1 register (PAGE0 -1Ah)....................................................................................... 134
6.19 Power control 2 register (PAGE0 -1Bh)....................................................................................... 135
6.20 Power control 3 register (PAGE0 -1Ch)....................................................................................... 136
6.21 Power control 4 register (PAGE0 -1Dh)....................................................................................... 136
6.22 Power control 5 register (PAGE0 -1Eh)....................................................................................... 137
6.23 Power control 6 register (PAGE0 -1Fh)....................................................................................... 138
6.24 Read data register (PAGE0 -22h)................................................................................................ 139
6.25 VCOM control 1~3 register (PAGE0 -23~25h) ............................................................................ 140
6.26 Display control 1 register (PAGE0 -26h~R28h)........................................................................... 143
6.27 Frame control register (PAGE0 -29h~R2Ch)............................................................................... 146
6.28 Cycle control register (PAGE0 -2Dh~R2Eh)................................................................................ 148
6.29 Display inversion register (PAGE0 -2Fh)..................................................................................... 149
6.30 RGB interface control register (PAGE0 -31h~R34h)................................................................... 150
6.31 Panel characteristic control register (PAGE0 -36h)..................................................................... 152
6.32 OTP register (PAGE0 -38h ~ R3Ah)............................................................................................ 153
6.33 CABC control 1~4 register (PAGE0 -3Ch~3Fh) .......................................................................... 154
6.34 Gamma control 1~35 register (PAGE0 -40h~5Dh)...................................................................... 156
6.35 TE control register (PAGE0 -60h, 84h~85h)................................................................................ 161
6.36 ID register (PAGE0 -R61h~R63h) ............................................................................................... 162
6.37 Power saving internal control register (PAGE0 -RE4h~RE7h).................................................... 163
6.38 Source OP control (PAGE0 -RE8h~E9h) .................................................................................... 164
6.39 Power control internal used (PAGE0 -REAh~ECh)..................................................................... 165
6.40 Command page select register (RFFh) ....................................................................................... 165
6.41 DGC Control register (PAGE1 -00h)............................................................................................ 166
6.42 DGC LUT register (PAGE1 -01h~63h) ........................................................................................ 166
6.43 CABC control 5~7 register (PAGE1 – RC3h, RC5h, RC7h)........................................................ 167
6.44 Gain select register 0~8 (PAGE1 – RCBh~D3h)......................................................................... 168
7. Layout Recommendation .................................................................................................................... 170
7.1 Maximum layout resistance ......................................................................................................... 171
7.2 External components connection ................................................................................................ 172
8. Electrical Characteristic ...................................................................................................................... 173
8.1 Absolute maximum ratings .......................................................................................................... 173
8.2 ESD protection level .................................................................................................................... 173
8.3 DC characteristics ....................................................................................................................... 174
8.4 Current consumption ................................................................................................................... 176
8.5 AC characteristics........................................................................................................................ 177
HX8347-G(T)
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
October, 2009
For 思泉 Only
-P.4-
Himax Confidential
October, 2009
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
8.5.1 Parallel interface characteristics (8080-series MPU) ......................................................... 177
8.5.2 Serial interface characteristics ........................................................................................... 180
8.5.3 RGB interface characteristics............................................................................................. 181
8.5.4 Reset input timing............................................................................................................... 183
9. Ordering Information............................................................................................................................ 184
10. Revision History ................................................................................................................................... 184
HX8347-G(T)
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
October, 2009
For 思泉 Only
-P.5-
Himax Confidential
October, 2009
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Figure 4.1: Register read/write timing in parallel bus system interface (for I80 series MPU) ........... 30
Figure 4.2: GRAM read/write timing in parallel bus system interface (for I80 series MPU).............. 31
Figure 4.3: Example of I80- system 18-bit parallel bus interface...................................................... 34
Figure 4.4: Input data bus and GRAM data mapping in 18-bit bus system interface with 18-bit-data
Input (“IM3, IM2, IM1, IM”=”1010” or “1000”)............................................................................. 34
Figure 4.5: Example of I80 system 16-bit parallel bus interface type I ............................................. 35
Figure 4.6: Example of I80 system 16-bit parallel bus interface type II ............................................ 35
Figure 4.7: Input data bus and GRAM data mapping in 16-bit bus system interface with 12-bit-data
input (R17H=03h and “IM3, IM2, IM1, IM0”=”0000”) ................................................................. 36
Figure 4.8: Input data bus and GRAM data mapping in 16-bit bus system interface with 16-bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0000”) ................................................................. 36
Figure 4.9: Input data bus and GRAM data mapping in 16-bit bus system interface with 18 bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”0000”) ................................................................. 36
Figure 4.10: Input data bus and GRAM data mapping in 16-bit bus system interface with 18(16+2)
bit-data input (R17H=07h and “IM3, IM2, IM1, IM0”=”0000”) .................................................... 36
Figure 4.11: Input data bus and GRAM data mapping in 16-bit bus system interface with 12-bit-data
input (R17H=03h and “IM3, IM2, IM1, IM0”=”0010”) ................................................................. 37
Figure 4.12: Input data bus and GRAM data mapping in 16-bit bus system interface with 16-bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0010”) ................................................................. 37
Figure 4.13: Input data bus and GRAM data mapping in 16-bit bus system interface with 18(12+6)
bit-data input (R17H=06h and “IM3, IM2, IM1, IM0”=”0010”) .................................................... 37
Figure 4.14: Input data bus and GRAM data mapping in 16-bit bus system interface with 18(16+2)
bit-data input (R17H=07h and “IM3, IM2, IM1, IM0”=”0010”) .................................................... 37
Figure 4.15: Example of I80 system 9-bit parallel bus interface type I ............................................. 38
Figure 4.16: Example of I80 system 9-bit parallel bus interface type II ............................................ 38
Figure 4.17: Input data bus and GRAM data mapping in 9-bit bus system interface with 18-bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”1001”) ................................................................. 39
Figure 4.18: Input data bus and GRAM data mapping in 9-bit bus system interface with 18-bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”1011”).................................................................. 39
Figure 4.19: Example of I80 system 8-bit parallel bus interface type I ............................................. 40
Figure 4.20: Example of I80 system 8-bit parallel bus interface type II ............................................ 40
Figure 4.21: Input data bus and GRAM data mapping in 8-bit bus system interface with 12-bit-data
input (R17H=03h and“IM3, IM2, IM1, IM0”=”0001”) .................................................................. 41
Figure 4.22: Input data bus and GRAM data mapping in 8-bit bus system interface with 16-bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0001”) ................................................................. 41
Figure 4.23: Input data bus and GRAM data mapping in 8-bit bus system interface with 18-bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”0001) .................................................................. 41
Figure 4.24: Input data bus and GRAM data mapping in 8-bit bus system interface with 12-bit-data
input (R17H=03h and“IM3, IM2, IM1, IM0”=”0011”)................................................................... 42
Figure 4.25: Input data bus and GRAM data mapping in 8-bit bus system interface with 16-bit-data
input (R17H=05h and “IM3, IM2, IM1, IM0”=”0011”).................................................................. 42
Figure 4.26: Input data bus and GRAM data mapping in 8-bit bus system interface with 18-bit-data
input (R17H=06h and “IM3, IM2, IM1, IM0”=”0011”).................................................................. 42
Figure 4.27: Index register read/write timing in 3-wire serial bus system interface.......................... 46
Figure 4.28: Data write timing in 3-wire serial bus system interface................................................. 47
Figure 4.29: Index register write timing in 4-wire serial bus system interface .................................. 48
Figure 4.30: Data write timing in 4-wire serial bus system interface................................................. 48
Figure 4.31: DOTCLK cycle .............................................................................................................. 49
Figure 4.32: RGB interface circuit input timing diagram ................................................................... 50
Figure 4.33: RGB mode timing diagram............................................................................................ 51
Figure 4.34: RGB 18-bit/pixel on 6-bit data width ............................................................................. 54
Figure 4.35: RGB 16-bit/pixel on 16-bit data width ........................................................................... 55
Figure 4.36: RGB 18-bit/pixel on 18-bit data width ........................................................................... 56
Figure 5.1: Image data sending order from host............................................................................... 58
HX8347-G(T)
240RGB x 320 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
October, 2009
For 思泉 Only
