LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT11 IS
PORT(CLK:IN STD_LOGIC;
K_XOR,K1,K2:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE bhv OF CNT11 IS
SIGNAL C1,C2:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL M1,M2:STD_LOGIC;
BEGIN
PROCESS(CLK,C1)
BEGIN
IF RISING_EDGE(CLK) THEN
IF(C1="100")THEN C1<="000";
ELSE C1<=C1+1;END IF;
IF(C1="000")THEN M1<=NOT M1;
ELSIF(C1="010")AND FALLING_EDGE(CLK)THEN
M1<=NOT M1;
END IF;END IF;
END PROCESS;
PROCESS(CLK,C2)
BEGIN
IF FALLING_EDGE(CLK) THEN
IF(C2="100")THEN C2<="000";
ELSE C2<=C1+1;END IF;
IF(C2="000") THEN M2<=NOT M2;
ELSIF(C2="011")AND RISING_EDGE(CLK)THEN
M2<=NOT M2;
END IF;END IF;
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