Design Guide Intel Confidential 5
5.4.4 DisplayPort* Auxiliary Channel (AUX CH) General Design Considerations and
Optimization........................................................................................ 197
5.5 DisplayPort* Length Matching Guidelines ............................................................ 199
5.6 Digital Display Interface Disabling and Termination Guidelines............................... 199
5.7 Display Compensation Guidelines ...................................................................... 199
6 Embedded DisplayPort* (eDP*) Design Guidelines ................................................ 200
6.1 Signal Descriptions .......................................................................................... 200
6.2 Topology Guidelines......................................................................................... 200
6.3 Optimizations ................................................................................................. 201
6.3.1 Kaby Lake Processor Graphics Embedded DisplayPort* Main Link Topology for
HBR and HBR2..................................................................................... 202
6.3.2 Kaby Lake Processor Graphics eDP* Auxiliary Channel Topology ................. 203
6.3.3 Embedded DisplayPort* Hot-Plug Detect Implementation........................... 203
6.4 Length Matching Guidelines .............................................................................. 204
6.5 Digital Display Interface Compensation Guidelines ............................................... 204
6.5.1 Compensation Signal Routing Guidelines ................................................. 205
6.5.2 Disabling and Termination Guidelines ...................................................... 205
7 High-Definition Multimedia Interface* (HDMI*) Design Guidelines ....................... 206
7.1 Overview ....................................................................................................... 206
7.2 Signal Description ........................................................................................... 209
7.3 HDMI 1.4* Topology Guidelines......................................................................... 209
7.3.1 Differential-Pair Width and Spacing......................................................... 209
7.3.2 Optimizations ...................................................................................... 209
7.3.3 HDMI 1.4* Main Link Cost-reduced Level Shifter and Active Level Shifter
Topologies........................................................................................... 210
7.3.4 HDMI 1.4* Main Link Active Level Shifter Docking Topologies ..................... 212
7.3.5 HDMI 1.4*Active Level Shifter Motherboard with Passive Multiplexer ........... 214
7.3.6 HDMI 1.4* Internal Cabled Solution ........................................................ 215
7.3.7 HDMI 1.4* (DDC) Signals Design Guidelines ............................................ 216
7.3.8 HDMI 1.4* DDC Signals on Motherboard Topologies with Cost-reduced Level
Shifter, Active Level Shifter and Docking Active Level Shifter...................... 217
7.3.9 HDMI 1.4* HPD Implementation............................................................. 219
7.4 HDMI* 2.0 Topology Guidelines......................................................................... 220
7.4.1 HDMI 2.0* HPD Implementation............................................................. 224
7.5 Digital Display Interface Disabling and Termination Guidelines............................... 224
7.6 Display Compensation Guidelines ...................................................................... 224
8 Switchable Graphics Design Guidelines for Kaby Lake UR U MCP Platforms ........... 225
8.1 Introduction ................................................................................................... 225
8.2 Switchable Graphics Additional Guidelines........................................................... 226
8.2.1 GPIO Selection Criteria.......................................................................... 226
9 Thunderbolt™ Design Guidelines ........................................................................... 228
9.1 Supported Thunderbolt™ Configuration Options................................................... 229
9.2 Port Power Requirements ................................................................................. 229
9.2.1 Host Source Requirements .................................................................... 229
9.3 Power Delivery................................................................................................ 230
9.3.1 Power Provider VBUS Electrical Requirements........................................... 230
9.3.2 VCONN Source Electrical Requirements ................................................... 230
9.3.3 BIOS .................................................................................................. 231
9.3.4 Reference Documents ........................................................................... 233
9.3.5 Compliance Specification ....................................................................... 233
9.3.6 Signal Descriptions ............................................................................... 233
9.4 Topology Guidelines......................................................................................... 234
9.4.1 Motherboard Down Topology.................................................................. 234