3.6 Register accesses in AArch32 state ........................................................................ 3-70
3.7 Predeclared core register names in AArch32 state ........................ ........................ 3-71
3.8 Predeclared extension register names in AArch32 state .................... .................... 3-72
3.9 Program Counter in AArch32 state .......................................................................... 3-73
3.10 The Q flag in AArch32 state .................................................................................... 3-74
3.11 Application Program Status Register ................................... ................................... 3-75
3.12 Current Program Status Register in AArch32 state ........................ ........................ 3-76
3.13 Saved Program Status Registers in AArch32 state ........................ ........................ 3-77
3.14 A32 and T32 instruction set overview ...................................................................... 3-78
3.15 Access to the inline barrel shifter in AArch32 state ........................ ........................ 3-79
Chapter 4 Overview of AArch64 state
4.1 Registers in AArch64 state ...................................................................................... 4-81
4.2 Exception levels ................................................... ................................................... 4-82
4.3 Link registers ..................................................... ..................................................... 4-83
4.4 Stack Pointer register .............................................................................................. 4-84
4.5 Predeclared core register names in AArch64 state ........................ ........................ 4-85
4.6 Predeclared extension register names in AArch64 state .................... .................... 4-86
4.7 Program Counter in AArch64 state .......................................................................... 4-87
4.8 Conditional execution in AArch64 state ................................. ................................. 4-88
4.9 The Q flag in AArch64 state .................................................................................... 4-89
4.10 Process State .......................................................................................................... 4-90
4.11 Saved Program Status Registers in AArch64 state ........................ ........................ 4-91
4.12 A64 instruction set overview .................................................................................... 4-92
Chapter 5 Structure of Assembly Language Modules
5.1 Syntax of source lines in assembly language .......................................................... 5-94
5.2 Literals .......................................................... .......................................................... 5-96
5.3 ELF sections and the AREA directive ...................................................................... 5-97
5.4 An example Arm assembly language module ............................ ............................ 5-98
Chapter 6 Writing A32/T32 Assembly Language
6.1 About the Unified Assembler Language ................................................................ 6-102
6.2 Syntax differences between UAL and A64 assembly language ............................ 6-103
6.3 Register usage in subroutine calls .................................... .................................... 6-104
6.4 Load immediate values .......................................................................................... 6-105
6.5 Load immediate values using MOV and MVN ........................... ........................... 6-106
6.6 Load immediate values using MOV32 ................................. ................................. 6-109
6.7 Load immediate values using LDR Rd, =const ...................................................... 6-110
6.8 Literal pools ............................................................................................................ 6-111
6.9 Load addresses into registers ................................................................................ 6-113
6.10 Load addresses to a register using ADR ............................... ............................... 6-114
6.11 Load addresses to a register using ADRL .............................. .............................. 6-116
6.12 Load addresses to a register using LDR Rd, =label .............................................. 6-117
6.13 Other ways to load and store registers .................................................................. 6-119
6.14 Load and store multiple register instructions ............................ ............................ 6-120
6.15 Load and store multiple register instructions in A32 and T32 ................................ 6-121
6.16 Stack implementation using LDM and STM ............................. ............................. 6-122
6.17 Stack operations for nested subroutines ............................... ............................... 6-124
6.18 Block copy with LDM and STM .............................................................................. 6-125
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