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J750 Hardware Specifications
Rev 1.95 4/27/2001
Aurora Hardware Specifications 04/30/01 7:41 AM
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Table of Contents
1. Overview............................................................................... 5
1.1 Environmental................................................................ 5
1.2 Channel count................................................................ 5
2. Vector Rate........................................................................... 5
3. Channel Specifications ......................................................... 5
3.1 VIL and VIH Driver Levels ............................................. 5
3.1.1 Voltage ranges ....................................................... 5
3.1.2 Output Impedance.................................................. 6
3.1.3 Minimum Pulse Width ............................................ 6
3.1.4 Waveform Fidelity................................................... 6
3.1.5 Rise/Fall Time ........................................................ 6
3.2 COMPARATOR SPECIFICATIONS.............................. 6
3.2.1 VOL and VOH Comparator Levels ......................... 6
3.2.2 Input Leakage......................................................... 6
3.2.3 Device Loading....................................................... 7
3.2.4 Slow Risetime Loading ........................................... 8
3.2.5 Comparator Waveform Fidelity .............................. 9
3.3 DYNAMIC LOAD SPECIFICATIONS ............................ 9
3.3.1 IOL and IOH Current Levels................................... 9
3.3.2 Theshhold (Vt) Voltage Levels ............................... 9
3.3.3 Load Input Resistance, DC .................................... 9
3.3.4 Settling Time .......................................................... 9
3.4 Voltage Clamps ............................................................. 9
3.5 High Voltage Drivers.................................................... 10
3.5.1 Channels .............................................................. 10
3.5.2 Voltage range (Vihh)............................................. 10
3.5.3 Rise Time ............................................................. 10
3.5.4 Current Limit......................................................... 10
3.5.5 Current Sink Capability......................................... 10
3.5.6 Maximum Overshoot ............................................ 10
3.5.7 Maximum Source Impedance .............................. 10
4. PIN PARAMETRIC MEASUREMENT UNIT (PPMU) ......... 11
4.1 Voltage Forcing/Measuring (No load) .......................... 11
4.2 Current Forcing Ranges .............................................. 11
4.3 Current Measuring Ranges ......................................... 11
5. TIMING GENERATION ...................................................... 11
Aurora Hardware Specifications 04/30/01 7:41 AM
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5.1 Clock Generation......................................................... 11
5.2 Period Generation........................................................ 11
5.3 Multiple Clocks............................................................. 11
5.4 Edge Generation.......................................................... 12
5.4.1 Timing Generators per Channel (normal mode) .. 12
5.4.2 Timing Generators per Channel (extended mode)12
5.5 Timing Sets.................................................................. 12
5.5.1 Number of timing sets .......................................... 12
5.5.2 Formatting Capabilities......................................... 13
5.6 Drive Formats .............................................................. 13
5.7 Compare Formats........................................................ 13
5.8 Pass/Fail Generation ................................................... 13
5.9 Channel Output Initialization........................................ 14
5.10 Edge Range................................................................. 14
5.10.1 Edge Resolution ................................................... 14
5.11 Edge Placement Accuracy........................................... 14
5.11.1 Edge Restrictions ................................................. 14
6. Digital Vectors..................................................................... 14
6.1 Number Of Digital Vectors........................................... 14
6.2 Pattern Data States ..................................................... 15
6.3 Scan Testing................................................................ 15
6.3.1 Scan depth per 64 channels (4 Meg system)...... 15
6.4 Pattern Control............................................................. 15
6.4.1 Microcode Memory Depth .................................... 15
6.4.2 Cycle Counter....................................................... 15
6.4.3 Fail Counter .......................................................... 15
6.4.4 Debug Features.................................................... 15
6.4.5 Keep Alive Operation............................................ 16
7. PMU SPECIFICATION LIST............................................... 18
7.1 Voltage Forcing:........................................................... 18
7.2 Voltage Measuring....................................................... 18
7.3 Current Forcing............................................................ 18
7.4 Current Measuring....................................................... 18
7.5 Programmable Clamps................................................ 19
7.5.1 Voltage Clamp...................................................... 19
7.5.2 Current Limit......................................................... 19
7.6 PMU SUPPLEMENTAL CHARACTERISTICS............ 19
8. Converter Test Option (High Accuracy Voltage)................. 20
8.1 Voltage Forcing:........................................................... 20
8.2 Voltage Measuring....................................................... 20
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9. Device Power Supplies ....................................................... 21
9.1 Voltage Forcing............................................................ 21
9.1.1 Voltage Settling .................................................... 21
9.2 Output Current Range ................................................. 21
9.3 Current Measuring....................................................... 21
9.4 DPS Supplemental Characteristics ............................. 21
10. DIB Utility......................................................................... 22
10.1 Utility Power................................................................. 22
10.2 Utility Bits ..................................................................... 22
11. Memory Test Option........................................................ 22
11.1 Pattern Rate................................................................. 22
11.2 Address Generation..................................................... 22
11.3 Data Generation .......................................................... 24
11.3.1 16 Bit Data Generator .......................................... 24
11.3.2 2 Bit Data Generator ............................................ 25
11.4 Utility Counters ............................................................ 25
11.5 Algorithmic Pattern Input/Output and Configurations .. 26
11.6 Capture Memory.......................................................... 26
11.7 Map Memory................................................................ 26
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1. OVERVIEW
The J750 is a 512 or 1024 channel test system, contained entirely in the test head.
1.1 Environmental
20 to 30 degrees C and 40-60 % humidity non-condensing .
A temperature change of 5 Degrees C will require internal re-calibration.
1.2 Channel count
The minimum system configuration is 64 channels. The system is expandable in 64 channel
increments. The maximum system is either 512 channels or 1024 channels, depending on tester
model.
2. Vector Rate
The base vector rate for the system in normal mode allows full functionality on all channels at
100Mhz.
A special "extended" mode provides additional capabilities when the vector rate is restricted to
50MHz. Multiplexing pairs of channels doubles the extended mode data rate to 100 Mhz with full
functionality but lower channel count.
3. Channel Specifications
A Spice model will be available upon request. The measurement convention is:
Positive current flows into the device under test from the tester. Negative current flows
out of the device under test. Thus IOL is always positive, and IOH is negative. The level
names correspond to the device usage, thus the Device Voltage Input Low is the
tester’s drive low level.
Level change settling time: 1.28ms, for Channel Levels
3.1 VIL and VIH Driver Levels
3.1.1 Voltage ranges
Range Resolution Accuracy
Vil -1 to +6V 1mv ± 15 mV
Vih 0 to +7.1V 1mv ± 15 mV
Minimum Difference: Vih >= (Vil + 0.1)
DC Output Current Hi Source/Low Sink 35 mA min.
Dynamic drive current 100ma Typ.
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