AST2600 Datasheet

AST2600

Integrated Remote Management Processor

A3 Datasheet

ASPEED Technology Inc.

Version 0.9

May 6, 2021

ASPEED Technology Inc. retains the right to make changes to its products or specifications. While

the information furnished herein is held to be accurate and reliable, no responsibility will be assumed

by ASPEED Technology for its use. Furthermore, the information contained herein does not convey to

holders.

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Copyright ©2021, ASPEED Technology Inc. All right reserved.

ASPEED AST2600 A3 Datasheet – V0.9

Ordering Information

ASPEED AST2600 A3 Datasheet – V0.9

Sep.12, 2019 0.3 1. Merge R3VDD and R4VDD into one ”RVDD” power domain.

2. Change PV33D ”Pin K11” and ”Pin K12” to indepent ”PV33D RGM” do-

main.

3. Add Electrical Specifications.

4. Fix some typo.

Nov. 21, 2019 0.4 1. Correct WDTRST and RSTIND signal name with low active symbol.

2. Remove BMCINT function on Pin A15.

3. Add new HBLED# function on Pin Y23.

4. First release for AST2600 A1.

Jan. 3, 2020 0.5 1. Add section ”Reset Source Table”.

SCU314[12:6], SCU338, SCU33C, SCU500, SCU510, SCUC20[18:16] de-

tail descriptions.

2. Add OTP Memory descriptions in section 61.

3. Add new MAC58[28] and MAC58[27] register descriptions.

4. Modify I2CD04[19:16] and I2CD04[15:12] register descriptions.

5. Change desciprtions for Uart Debug Interface section 11.

6. Remove interrupt #197 from interrupt source table in section 8.

7. Remove register SWVIC10, SWVIC18[15], SWVIC1C[15], SWVIC20,

SWVIC28[15], SWVIC2C[15].

8. Add new function LPC Mem/FWH to AHB with register HICR6[17].

13. Add SCU to Strap Source Mappings to represent the strap sources

clearly.

14. Update VR040 Multi-JPEG Data Buffer descriptions.

15. Change feature of Master Serial GPIO to 2 sets

16. Change feature of Slave Serial GPIO to 2 sets

17. Add new section 9 ”Hardware Strap Registers”

18. Add new section 10 ”ARM TrustZone”

19. Add OTP programming temperature SPEC.

20. Add SPI electical SPEC when clock speed higher than 100MHz.

21. Add RSTIND# electrical SPEC on power sequence section.

ASPEED AST2600 A3 Datasheet – V0.9

Aug.18, 2020 0.7 1. Add watchdog related protection registers for security: SCU830, SCU834,

SCU850, SCU854, SCU858, SCU85C, SCU870, SCU874, SCU878,

SCU87C.

2. Add seperated UART DMA control registers: UDMA04C, UDMA05C,

UDMA06C, UDMA07C, UDMA08C, UDMA09C, UDMA0AC, UDMA0BC,

UDMA0CC, UDMA0DC, UDMA0EC, UDM0FC, UDMA10C, UDMA11C,

UDMA12C, UDMA13C, UDMA14C, UDMA15C, UDMA16C, UDMA17C,

UDMA18C, UDM19C, UDMA1AC, UDMA1BC, UDMA1CC, UDMA1DC,

UDMA1EC, UDMA1FC. And increased buffer size for VUART TX/RX DMA.

3. Add 4 independent I2C controllers for security usage (I2CS) 53. And Add

6. Add new hardware pin straps: GPIOZ3, GPIOZ4, GPIOZ5, GPIOZ6,

GPIOZ7 in 2.3 and update register SCU51C[10:6].

7. Add core power good and I/O power good detection registers and CHASI#

raw status to register CHAI10

8. Add detail I3C Register revision change in Section 54.3

9. Remove LPC Host function.

10. Update ”I/O DC Electrical Specification” for A2 version.

11. Add and modify PTCR0F0[20], ACPIE3E0, ACPIE3, MBXSTS0,

MBXBCR, MBXFCR1, MBXFCR2, SMBXFCR1, SMBXFCR2, HICR6,

HICR9, HICRA, SV1UART24, SIRQCR0, SIRQCR1, SIRQCR2, SIRQCR3,

4. Correct timing control block diagram for MAC1/MAC2/MAC3/MAC4.

5. Add NCSI 50MHz clock output frequency stability from PinF24/PinH24.

6. Add minimum pulse timing requirement for CHASI#.

7. Fix some typo.

ASPEED AST2600 A3 Datasheet – V0.9

May.6, 2021 0.9 1. Add description of behavior of OOB FREE in ESPI000[4].

2. Add A2 to A3 change notice.

3. Remove system reset control for AHB bridges, SCU040[1], and change to

reserve.

4. Provide OTP strap option, OTPSTRAP[23] and SCU500[24], to enable

PCIe root complex reset on SSPRST# pin.

5. Provide programming option, SCU040[18], to reset PCIe root complex

when OTPSTRAP[23]=0. (similar to dedicated reset pin).

6. Add revision ID for A3 in SCU004.

7. Change default values of SCU0C8 and SCU0D8. See details in ”A2 to A3

MAC 1 RGMII mode. The OTPSTRAP[6] should be MAC 2 RGMII mode. The

OTPSTRAP[32] should be MAC 3 RGMII mode. The OTPSTRAP[34] should

be MAC 4 RGMII mode.

10. Fix typo of the password in SEC00

11. Change SCUC08, PEHR04, SCUC24[9], HICRB[6], HICRB[29] ,

PECI00[24], PECI08[30].

12. Add I3C010[29], I3C010[28], I3C020[29], I3C020[28], I3C030[29],

I3C030[28], I3C040[29], I3C040[28], I3C050[29], I3C050[28], I3C060[29],

I3C060[28].

13. Add ADDR MASK, please refer to I3CD280, I3CD284, I3CD288,

17. Fix typo in Uart DMA, there are 14 sets of DMAs. The base address is

Uart DMA instead of Timer.

18. Fix baud rate calculation in UART Controller, UART DLL/UART DLH.

19. Fix typo of SDIO0F4[25:21] to Slot 1 Input Clock Phase.

20. Add PHYA00 and PHYB00[11] bit to enable lower transmit FIFO threshold

setting.

21. Add PHYA00 and PHYB00[10] bit to improve asynchronous list perfor-

mance.

22. Add more detail hardware strap description on Hardware Pin Strap Sec-

28. Remove description of

SEC78[3]. It is a typo.

Text color definition

2. A1 revision

3. A2/A3 revision

A1 to A2 Change Highlight: