GD32F1x0 User Manual
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6.3.8. GPIO locking function ......................................................................................................... 144
6.3.9. GPIO single cycle toggle function ....................................................................................... 144
6.4. Register definition ................................................................................................... 145
6.4.1. Port control register (GPIOx_CTL, x=A..D,F) ..................................................................... 145
6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..................................................... 146
6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F) ........................................................ 148
6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F) ........................................................... 150
6.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ........................................................... 151
6.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 152
6.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 152
6.4.8. Port configuration lock register (GPIOx_LOCK, x=A, B) .................................................... 153
6.4.9. Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C) ................................... 154
6.4.10. Alternate function selected register1 (GPIOx_AFSEL1, x=A,B,C) ..................................... 155
6.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 156
6.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F) (Only for GD32F170xx and GD32F190xx
devices) ............................................................................................................................................ 157
7. CRC calculation unit (CRC) ................................................................................. 158
7.1. Overview .................................................................................................................. 158
7.2. Characteristics ......................................................................................................... 158
7.3. Function overview ................................................................................................... 159
7.4. Register definition ................................................................................................... 161
7.4.1. Data Register (CRC_DATA)................................................................................................ 161
7.4.2. Free Data Register (CRC_FDATA) ..................................................................................... 161
7.4.3. Control Register (CRC_CTL) .............................................................................................. 162
7.4.4. Initialization Data Register (CRC_IDATA) ........................................................................... 162
8. Direct memory access controller (DMA) ............................................................ 164
8.1. Overview .................................................................................................................. 164
8.2. Characteristics ......................................................................................................... 164
8.3. Block diagram .......................................................................................................... 165
8.4. Function overview ................................................................................................... 165
8.4.1. DMA operation .................................................................................................................... 165
8.4.2. Peripheral handshake ......................................................................................................... 167
8.4.3. Arbitration ............................................................................................................................ 167
8.4.4. Address generation ............................................................................................................. 168
8.4.5. Circular mode...................................................................................................................... 168
8.4.6. Memory to memory mode ................................................................................................... 168
8.4.7. Channel configuration ......................................................................................................... 168
8.4.8. Interrupt ............................................................................................................................... 169
8.4.9. DMA request mapping ........................................................................................................ 170