C51增强型各种头文件

//----------------------------------------------------------------------------- // Si1000_defs.h //----------------------------------------------------------------------------- // Copyright 2010 Silicon Laboratories, Inc. // http://www.silabs.com // // Program Description: // // Register/bit definitions for the Si100x family. // // // Target: Si100x // Tool chain: Keil, SDCC // Command Line: None // // // Release 1.0 // -EZRadioPRO definitions created by Ken Berrenger. // -26 JAN 2010 (FB) // //----------------------------------------------------------------------------- // Header File Preprocessor Directive //----------------------------------------------------------------------------- #ifndef SI1000_DEFS_H #define SI1000_DEFS_H //----------------------------------------------------------------------------- // Byte Registers //----------------------------------------------------------------------------- SFR (P0, 0x80); // Port 0 Latch SFR (SP, 0x81); // Stack Pointer SFR (DPL, 0x82); // Data Pointer Low SFR (DPH, 0x83); // Data Pointer High SFR (SPI1CFG, 0x84); // SPI1 Configuration SFR (SPI1CKR, 0x85); // SPI1 Clock Rate Control SFR (TOFFL, 0x85); // Temperature Offset Low SFR (SPI1DAT, 0x86); // SPI1 Data SFR (TOFFH, 0x86); // Temperature Offset High SFR (PCON, 0x87); // Power Control SFR (TCON, 0x88); // Timer/Counter Control SFR (TMOD, 0x89); // Timer/Counter Mode SFR (TL0, 0x8A); // Timer/Counter 0 Low SFR (TL1, 0x8B); // Timer/Counter 1 Low SFR (TH0, 0x8C); // Timer/Counter 0 High SFR (TH1, 0x8D); // Timer/Counter 1 High SFR (CKCON, 0x8E); // Clock Control SFR (PSCTL, 0x8F); // Program Store R/W Control SFR (P1, 0x90); // Port 1 Latch SFR (TMR3CN, 0x91); // Timer/Counter 3 Control SFR (CRC0DAT, 0x91); // CRC0 Data SFR (TMR3RLL, 0x92); // Timer/Counter 3 Reload Low SFR (CRC0CN, 0x92); // CRC0 Control SFR (TMR3RLH, 0x93); // Timer/Counter 3 Reload High SFR (CRC0IN, 0x93); // CRC0 Input SFR (TMR3L, 0x94); // Timer/Counter 3 Low SFR (CRC0FLIP, 0x95); // CRC0 Flip SFR (TMR3H, 0x95); // Timer/Counter 3 High SFR (DC0CF, 0x96); // DC0 (DC/DC Converter) Configuration SFR (CRC0AUTO, 0x96); // CRC0 Automatic Control SFR (DC0CN, 0x97); // DC0 (DC/DC Converter) Control SFR (CRC0CNT, 0x97); // CRC0 Automatic Flash Sector Count SFR (SCON0, 0x98); // UART0 Control SFR (SBUF0, 0x99); // UART0 Data Buffer SFR (CPT1CN, 0x9A); // Comparator1 Control SFR (CPT0CN, 0x9B); // Comparator0 Control SFR (CPT1MD, 0x9C); // Comparator1 Mode Selection SFR (CPT0MD, 0x9D); // Comparator0 Mode Selection SFR (CPT1MX, 0x9E); // Comparator1 Mux Selection SFR (CPT0MX, 0x9F); // Comparator0 Mux Selection SFR (P2, 0xA0); // Port 2 Latch SFR (SPI0CFG, 0xA1); // SPI0 Configuration SFR (SPI0CKR, 0xA2); // SPI0 Clock Rate Control SFR (SPI0DAT, 0xA3); // SPI0 Data SFR (P0MDOUT, 0xA4); // Port 0 Output Mode Configuration SFR (P0DRV, 0xA4); // Port 0 Drive Strength SFR (P1MDOUT, 0xA5); // Port 1 Output Mode Configuration SFR (P1DRV, 0xA5); // Port 1 Drive Strength SFR (P2MDOUT, 0xA6); // Port 2 Output Mode Configuration SFR (P2DRV, 0xA6); // Port 2 Drive Strength SFR (SFRPAGE, 0xA7); // SFR Page SFR (IE, 0xA8); // Interrupt Enable SFR (CLKSEL, 0xA9); // Clock Select SFR (EMI0CN, 0xAA); // EMIF Control SFR (EMI0CF, 0xAB); // EMIF Configuration SFR (RTC0ADR, 0xAC); // RTC0 Address SFR (RTC0DAT, 0xAD); // RTC0 Data SFR (RTC0KEY, 0xAE); // RTC0 Key SFR (EMI0TC, 0xAF); // EMIF Timing Control SFR (ONESHOT, 0xAF); // ONESHOT Timing Control SFR (SPI1CN, 0xB0); // SPI1 Control SFR (OSCXCN, 0xB1); // External Oscillator Control SFR (OSCICN, 0xB2); // Internal Oscillator Control SFR (OSCICL, 0xB3); // Internal Oscillator Calibration SFR (PMU0CF, 0xB5); // PMU0 Configuration SFR (FLSCL, 0xB6); // Flash Scale Register SFR (FLKEY, 0xB7); // Flash Lock And Key SFR (IP, 0xB8); // Interrupt Priority SFR (IREF0CN, 0xB9); // Current Reference IREF0 Control SFR (ADC0AC, 0xBA); // ADC0 Accumulator Configuration SFR (ADC0PWR, 0xBA); // ADC0 Burst Mode Power-Up Time SFR (ADC0MX, 0xBB); // AMUX0 Channel Select SFR (ADC0CF, 0xBC); // ADC0 Configuration SFR (ADC0TK, 0xBD); // ADC0 Tracking Control SFR (ADC0L, 0xBD); // ADC0 Low SFR (ADC0H, 0xBE); // ADC0 High SFR (P1MASK, 0xBF); // Port 1 Mask SFR (SMB0CN, 0xC0); // SMBus0 Control SFR (SMB0CF, 0xC1); // SMBus0 Configuration SFR (SMB0DAT, 0xC2); // SMBus0 Data SFR (ADC0GTL, 0xC3); // ADC0 Greater-Than Compare Low SFR (ADC0GTH, 0xC4); // ADC0 Greater-Than Compare High SFR (ADC0LTL, 0xC5); // ADC0 Less-Than Compare Word Low SFR (ADC0LTH, 0xC6); // ADC0 Less-Than Compare Word High SFR (P0MASK, 0xC7); // Port 0 Mask SFR (TMR2CN, 0xC8); // Timer/Counter 2 Control SFR (REG0CN, 0xC9); // Voltage Regulator (REG0) Control SFR (TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low SFR (TMR2RLH, 0xCB); // Timer/Counter 2 Reload High SFR (TMR2L, 0xCC); // Timer/Counter 2 Low SFR (TMR2H, 0xCD); // Timer/Counter 2 High SFR (PCA0CPM5, 0xCE); // PCA0 Module 5 Mode Register SFR (P1MAT, 0xCF); // Port 1 Match SFR (PSW, 0xD0); // Program Status Word SFR (REF0CN, 0xD1); // Voltage Reference Control SFR (PCA0CPL5, 0xD2); // PCA0 Capture 5 Low SFR (PCA0CPH5, 0xD3); // PCA0 Capture 5 High SFR (P0SKIP, 0xD4); // Port 0 Skip SFR (P1SKIP, 0xD5); // Port 1 Skip SFR (P2SKIP, 0xD6); // Port 2 Skip SFR (P0MAT, 0xD7); // Port 0 Match SFR (PCA0CN, 0xD8); // PCA0 Control SFR (PCA0MD, 0xD9); // PCA0 Mode SFR (PCA0CPM0, 0xDA); // PCA0 Module 0 Mode Register SFR (PCA0CPM1, 0xDB); // PCA0 Module 1 Mode Register SFR (PCA0CPM2, 0xDC); // PCA0 Module 2 Mode Register SFR (PCA0CPM3, 0xDD); // PCA0 Module 3 Mode Register SFR (PCA0CPM4, 0xDE); // PCA0 Module 4 Mode Register SFR (PCA0PWM, 0xDF); // PCA0 PWM Configuration SFR (ACC, 0xE0); // Accumulator SFR (XBR0, 0xE1);