VHDL设计中优先级的重要性
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2015-06-03
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WP275 (v1.0.1) October 22, 2007 www.xilinx.com 1
© 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property
of their respective owners.
Would it be useful for your next design to be up to
50% smaller without significantly changing the ways
you do things now? In these cost-sensitive days, you
have to respond “yes”. This white paper describes a
rarely noticed design technique that can make a
difference in the size and the performance of your
FPGA design.
The ideas contained in this white paper might not
yield the full 50% savings potential in your design,
but should save a significant amount. A 20%
reduction in size can mean your design fits into a
smaller device. The smaller size also helps those
designers who are looking for higher performance
by potentially saving a speed grade.
This white paper provides some simple VHDL and
Verilog examples to explain key points. More VHDL
code examples are used due to the author’s
preference.
White Paper: Xilinx FPGA Families
WP275 (v1.0.1) October 22, 2007
Get your Priorities Right – Make
your Design Up to 50% Smaller
By: Ken Chapman
R
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