Verilog
HDL
仿
真
实
验
报
告
专业班级：
xxx
学 号： Uxxxxxxxxx
姓 名：
xxx
目录
Verilog HDL 仿真实验报告
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1
一、CD4532
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3
1. 设计代码
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3
2. 测试代码
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4
3. 仿真波形
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5
二、74X138
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5
1. 设计代码
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5
2. 测试代码
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6
3. 仿真波形
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7
三、74HC4511
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7
1. 设计代码
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7
2. 测试代码
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8
3. 仿真波形
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10
四、74HC151
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10
1. 设计代码
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10
2. 测试代码
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11
3. 仿真波形
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12
五、74HC85
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12
1. 设计代码
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12
2. 测试代码
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13
3. 仿真波形
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14
六、74HC283
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15
1. 设计代码
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15
2. 测试代码
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15
3. 仿真波形
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17
七、74HC/HCT194
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18
1. 设计代码
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18
2. 测试代码
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18
3. 仿真波形
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20
八、74LVC161
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20
1. 设计代码
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20
2. 测试代码
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21
3. 仿真波形
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22
九、用两片 CD4532 构成 16 线-4 线优先编码器
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22
1. 设计代码
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22
2. 测试代码
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23
3. 仿真波形
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26
十、5 线-32 线译码器
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26
1. 设计代码
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26
2. 测试代码
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28
3. 仿真波形
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29
十一、两片 74LS151 连接成 16 选 1 数据选择器
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29
1. 设计代码
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29
2. 测试代码
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30
3. 仿真波形
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32
十二、用两片 74HC85 组成 16 位数值比较器
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32
1. 设计代码
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32
2. 测试代码
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34
3. 仿真波形
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35
十三、篮球 24 秒计时显示器
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35
1. 设计代码
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35
2. 测试代码
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36
3. 仿真波形
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37
一、CD4532
1. 设计代码
module CD4532(EI,I,Y,GS,EO);
input EI;//使能信号EI
input [7:0] I;//输入信号0~7
output reg [2:0] Y;
output reg GS,EO;//输出信号
always @(*) begin
if(EI==0)begin//EI=0不使能
Y[2:0]=3'b000;
GS=0;
EO=0;
end
else begin//EI=0使能
GS=1;
EO=0;
casex(I[7:0])
8'b1xxxxxxx:Y[2:0]=3'b111;
8'b01xxxxxx:Y[2:0]=3'b110;
8'b001xxxxx:Y[2:0]=3'b101;
8'b0001xxxx:Y[2:0]=3'b100;
8'b00001xxx:Y[2:0]=3'b011;
8'b000001xx:Y[2:0]=3'b010;
8'b0000001x:Y[2:0]=3'b001;
8'b00000001:Y[2:0]=3'b000;
default begin//输入为0
GS=0;
EO=1;
Y[2:0]=3'b000;
end
endcase
end
end
endmodule
2. 测试代码
//filename CD4532_test.v
`timescale 10ns/1ns
module test_CD4532;
reg [7:0] I;
reg EI;
wire [2:0]Y;
wire GS,EO;
CD4532 U0(EI,I,Y,GS,EO);//实例化元件
initial
$monitor($time,"\tI=%b,EI=%b,EO=%b,GS=%b,Y=%b\n",I,EI,EO,GS,Y);
initial begin
EI = 0; I=8'b0000_0000; //使能信号EI不使能时
#1
I=8'b0000_0001;
#1
I=8'b0000_0010;
#1
I=8'b0000_0100;
#1
I=8'b0000_1000;
#1
I=8'b0001_0000;
#1
I=8'b0010_0000;
#1
I=8'b0100_0000;
#1
I=8'b1000_0000;
#1
EI=1; I=8'b000_0000; //使能信号EI使能时
#1
I=8'b0000_0001;
#1
I=8'b0000_0010;
#1
I=8'b0000_0100;
#1
I=8'b0000_1000;
#1
I=8'b0001_0000;
#1
I=8'b0010_0000;
#1
I=8'b0100_0000;
#1
I=8'b1000_0000;
#1 $stop;
end
endmodule
3. 仿真波形
二、74X138
1. 设计代码
module _74X138(E,A,Y);
input [2:0] E;//使能信号
input [2:0] A;//输入三比特信号
output reg [7:0] Y;//输出译码后的信号（低电平）
always @(*) begin
if(E == 3'b100) begin//使能时
casex(A[2:0])//输出相应低电平有效
3'b000:Y[7:0]=8'b1111_1110;
