JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD79-3E
July 2010
JEDEC
STANDARD
DDR3 SDRAM Specification
(Revision of JESD79-3D, August 2009)
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
www.jedec.org
Published by
©JEDEC Solid State Technology Association 2010
3103 North 10th Street, Suite 240 South
Arlington, VA 22201
This document may be downloaded free of charge; however JEDEC retains the copyright on this
material. By downloading this file the individual agrees not to charge for or resell the resulting
material.
PRICE: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications online at
http://www.jedec.org/Catalog/catalog.cfm
Printed in the U.S.A.
All rights reserved
PLEASE!
DON'T VIOLATE THE LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street, Suite 240 South
Arlington, Virginia 22201
or call (703) 907-7559
JEDEC Standard No. 79-3E
Contents
i
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
2.2 DDR3 SDRAM x8 Ballout using MO-207........................................................................4
2.3 DDR3 SDRAM x16 Ballout using MO-207......................................................................5
2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207..........................................6
2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207..........................................7
2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207........................................8
2.7 Quad-stacked / Quad-die DDR3 SDRAM x4 Ballout using MO-207...............................9
2.8 Quad-stacked / Quad-die DDR3 SDRAM x8 Ballout using MO-207.............................10
2.9 Quad-stacked / Quad-die DDR3 SDRAM x16 Ballout using MO-207...........................11
2.10 Pinout Description..........................................................................................................13
2.11 DDR3 SDRAM Addressing...........................................................................................15
2.11.1 512Mb ....................................................................................................................15
2.11.2 1Gb..........................................................................................................................15
2.11.3 2Gb .........................................................................................................................15
2.11.4 4Gb .........................................................................................................................15
2.11.5 8Gb .........................................................................................................................16
3 Functional Description.............................................................................................................17
3.1 Simplified State Diagram.................................................................................................17
3.2 Basic Functionality ..........................................................................................................18
3.3 RESET and Initialization Procedure ................................................................................19
3.3.1 Power-up Initialization Sequence .............................................................................19
3.3.2 Reset Initialization with Stable Power......................................................................21
3.4 Register Definition...........................................................................................................22
3.4.1 Programming the Mode Registers ............................................................................22
3.4.2 Mode Register MR0..................................................................................................23
3.4.3 Mode Register MR1..................................................................................................27
3.4.4 Mode Register MR2..................................................................................................30
3.4.5 Mode Register MR3..................................................................................................32
4 DDR3 SDRAM Command Description and Operation...........................................................33
4.1 Command Truth Table .....................................................................................................33
4.2 CKE Truth Table..............................................................................................................35
4.3 No OPeration (NOP) Command ......................................................................................36
4.4 Deselect Command ..........................................................................................................36
4.5 DLL-off Mode..................................................................................................................37
4.6 DLL on/off switching procedure......................................................................................38
4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
4.7 Input clock frequency change ..........................................................................................40
4.8 Write Leveling .................................................................................................................42
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
4.8.2 Procedure Description...............................................................................................43
4.8.3 Write Leveling Mode Exit ........................................................................................45
