紫光同创 Gamma 变换工程源代码（Verilog）

Instances in group: gopA2 N9_0_15/gateop_A2 gopA2 N9_0_21/gateop_A2 gopA2 N9_0_23/gateop_A2 gopA N9_0_27/gateop gopIBUF clock_reset_gen_inst/GTP_INBUFG_inst/opit_0 gopIBUFIOL clock_reset_gen_inst/GTP_INBUFG_inst/opit_0_iol gopA2Q2 clock_reset_gen_inst/reset_cnt[2]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[4]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[6]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[8]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[10]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[12]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[14]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[16]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[18]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[20]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[22]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[24]/opit_0_inv_A2Q21 gopA2Q2 clock_reset_gen_inst/reset_cnt[26]/opit_0_inv_A2Q21 gopAQ clock_reset_gen_inst/reset_cnt[27]/opit_0_inv_AQ gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/N266_1_1/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/N266_1_3/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_ddrc_top/u_ipsl_ddrc_reset_ctrl/u_ipsl_ddrc_apb_reset/N266_1_5/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N7.eq_0/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N7.eq_2/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N15_1.fsub_1/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N15_1.fsub_3/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N15_1.fsub_5/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N18_1_1/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N18_1_3/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N18_1_5/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N20.lt_0/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N20.lt_2/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N22.lt_0/gateop_A2 gopA2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ddrphy_update_ctrl/N22.lt_2/gateop_A2 gopA2Q2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/cnt[2]/opit_0_inv_A2Q21 gopA2Q2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/cnt[4]/opit_0_inv_A2Q21 gopA2Q2 ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/cnt[6]/opit_0_inv_A2Q21 gopAQ ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_ddrphy_reset_ctrl/cnt[7]/opit_0_inv_AQ gopIOBUFDSA ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/genblk2.iob_08_09_dut/opit_0 gopIOBUFDSB ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/genblk2.iob_08_09_dut/opit_1 gopIOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/genblk2.iob_08_09_dut/opit_2_O gopIOBUFDSA ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/genblk3.iob_30_31_dut/opit_0 gopIOBUFDSB ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/genblk3.iob_30_31_dut/opit_1 gopIOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/genblk3.iob_30_31_dut/opit_2_O gopIBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_00_dut/opit_0 gopIBUFIOL ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_00_dut/opit_0_iol gopOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_01_dut/opit_0 gopOBUFIOL ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_01_dut/opit_1 gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_02_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_02_dut/opit_1_IOL gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_03_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_04_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_05_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_06_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_07_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_10_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_11_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_12_dut/opit_0 gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_16_17_dut/opit_0 gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_16_17_dut/opit_1 gopIOLOTCMP ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_16_17_dut/opit_2 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_16_17_dut/opit_3_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_18_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_18_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_19_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_19_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_20_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_20_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_21_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_21_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_22_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_22_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_23_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_23_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_24_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_24_dut/opit_1_IOL gopOBUFT ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_25_dut/opit_0 gopOMDDR ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_25_dut/opit_1_IOL gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc_phy_top/u_ipsl_phy_io/iob_27_dut/opit_0 gopIOBUF ddr_scheduler_inst/ddr3_controller_inst/u_ipsl_hmemc