Quartus EMIF DDR3 IP 仿真工程

############################################################################### What is this? ############################################################################### This is the readme.txt file for the example design file set of the Intel External Memory Interface IP. Files in this directory allow you to do the following: 1) Create a Quartus Prime project that instantiates an external memory interface (same configuration as what you specified in the graphical user interface) and an example traffic generator. Once the design is created, you can optionally specify the target device and pin location assignments, run a full compilation using the Quartus Prime software, verify timing closure, and test the interface on your board using the programming file generated by the Quartus Prime assembler. 2) Create simulation projects for various supported simulators. The simulation projects instantiate an external memory interface (same configuration as what you specified in the graphical user interface), an example traffic generator, and an example memory model. Once the projects are generated, you can run simulation and use the results as a way to understand the behavior of the external memory interface IP. This flow only supports functional simulation. Timing simulation is not supported, and you must use static timing analysis provided by the TimeQuest software to verify timing closure. 3) Create collateral for performing signal integrity simulations of the external I/O channel for your memory interface. SPICE simulation decks are created that match your memory topology and I/O buffer settings, and you supply extractions of your PCB as well as IBIS models for the FPGA and memory and plug them into the simulation environment. Compliance masks for eye diagrams are also supplied by the IP to evaluate whether or not you have sufficent margin on the address/ command bus, the FPGA->Memory data write channel, and the Memory->FPGA data read channel. Note that this feature is only available for Agilex series IP and later. ############################################################################### Generating a Quartus Prime Example Design ############################################################################### To generate a Quartus Prime example design, run: quartus_sh -t make_qii_design.tcl To specify an exact device to use, run: quartus_sh -t make_qii_design.tcl [device_name] The generated example design is stored under the "qii" sub-directory. To re-generate the design, simply delete the "qii" sub-directory, and re-run the commands above. ############################################################################### Generating a Simulation Example Design ############################################################################### To generate simulation example designs for a Verilog or a mixed-language simulator, run: quartus_sh -t make_sim_design.tcl VERILOG To generate simulation example designs for a VHDL-only simulator, run: quartus_sh -t make_sim_design.tcl VHDL The generated example designs for various simulators are stored under the "ed_sim" sub-directory. For example, to run simulation using Synopsys' VCS, run: cd sim/ed_sim/synopsys/vcs ./vcs_setup.sh ############################################################################### Generating Board Signal Integrity Simulation Collateral ############################################################################### To generate SPICE simulation collateral, run: quartus_sh -t make_bsi_design.tcl The generated example design is stored under the "bsi" sub-directory. To re-generate the design, simply delete the "bsi" sub-directory, and re-run the commands above.