library ieee;
use ieee.std_logic_1164.all ;
entity ex1 is
port (din: in std_logic_vector (2 downto 0);
dout: out std_logic_vector (3 downto
0));
end ex1 ;
architecture rtl of ex1 is
begin
case (din) is
when “00” => dout <=“0001” ;
when “01” => dout <= “0010” ;
when “10” => dout <=“0100” ;
when “11” => dout <=“1000” ;
end case;
end rtl ;
1 、易犯的几个典型错误