Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
1 Publication Order Number:
MC14051B/D
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V
DD
– V
EE
) = 3.0 to 18 V
Note: V
EE
must be V
SS
• Linearized Transfer Characteristics
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
• For Lower R
ON
, Use the HC4051, HC4052, or HC4053 High–Speed
CMOS Devices
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage (Referenced
to V
EE
, V
SS
≥ V
EE
)
–0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient) (Referen–
ced to V
SS
for Control Inputs
and V
EE
for Switch I/O)
–0.5 to V
DD
+ 0.5 V
I
in
Input Current (DC or Transient)
per Control Pin
±10 mA
I
SW
Switch Through Current ±25 mA
P
D
Power Dissipation,
per Package (Note 2.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
, V
EE
or V
DD
). Unused outputs must be left open.
http://onsemi.com
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
140xxB
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC140xxB
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
14
0xxB
ALYW
1
16
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
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