HI3516DV500DMEB-VER-C-SCH中 DV500原理图
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2023-07-13
09:50:05
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Pull-up disable PLL@ALDPS mode
TXDLY=1 Add 2ns delay to TXC for TXD latching
Enable/Disable PLL @ ALDPS
Reserve capacitance For EMI
100M active&link
1000M active&link
PHY Address Config.
RGMII0 Voltage Config.
External Source
ETH
Close to PIN21
Close to PIN3，PIN8,PIN38
Internal 1.8V 1'b0 2'b10
CFG_EXT CFG_LDO[1:0]
External 3.3V(default) 1'b1 2'b00
Phy Address=001
RGMII0 TXC/RXC Delay Config.
RGMII0 Power Source
External 1.8V 1'b1 2'b10
1
PHYAD[2:0]
3'b001 (default)
PHY Address
RXDLY=1 Add 2ns delay to RXC for RXD latching
位号：7200
3V3_PER
3V3_PER
DVDD_ETHIO
3V3_PER
DVDD_ETHIO
DVDD_ETHIO
DVDD_ETHIO
DVDD_ETHIO
DVDD_ETHIO
1 2 3 4 5 6
1
A
D
B
C
A
D
B
C
2
3
4
5
6
REVIEWED
DESIGNED
VER PART_NUMBER
The type and specification of the components refer to the BOM
DATEECA NO
SHEET OF
C
Hi3516DV500DMEB
11
NA
29
1 2 3 4 5 6
1
A
D
B
C
A
D
B
C
2
3
4
5
6
REVIEWED
DESIGNED
VER PART_NUMBER
The type and specification of the components refer to the BOM
DATEECA NO
SHEET OF
C
Hi3516DV500DMEB
11
NA
29
1 2 3 4 5 6
1
A
D
B
C
A
D
B
C
2
3
4
5
6
REVIEWED
DESIGNED
VER PART_NUMBER
The type and specification of the components refer to the BOM
DATEECA NO
SHEET OF
C
Hi3516DV500DMEB
11
NA
29
L7200
2.2UH
R7214
22
RTL8211FI-CG
U7200
MDIP0
1
MDIN0
2
AVDD10_1
3
MDIP1
4
MDIN1
5
MDIP2
6
MDIN2
7
AVDD10_2
8
MDIP3
9
MDIN3
10
AVDD33_1
11
PHYRSTB
12
MDC
13
MDIO
14
TXD3
15
TXD2
16
TXD1
17
TXD0
18
TXCTL
19
TXCLK
20
DVDD10
21
RXD3/PHYAD0
22
RXD2/PLLOFF
23
RXD1/TXDLY
24
RXD0/RXDLY
25
RXCTL/PHY_AD2
26
RXC/PHYAD1
27
DVDD_RG
28
DVDD33
29
REG_OUT/LDO_OUT
30
INTB/PMEB
31
LED0/CFG_EXT
32
LED1/CFG_LDO0
33
LED2/CFG_LDO1
34
CLKOUT
35
XTAL_IN
36
XTAL_OUT/EXT_CLK
37
AVDD10_3
38
RSET
39
AVDD33_2
40
GND
41
C7216100NF
R7216
2.49K
R7212
4.7K
C7213100NF
R7219
0
C723339PF
C721810uF
R7201
4.7K
C72256PF/NC*
R7208
22
C7222
22PF
C72296PF/NC*
R7200
4.7K
LB7204
1 2
R7221 0/NC*
C721710uF
R7220 0
C7212100NF
C72051NF
R7218
4.7K
C721910uF
LB7203
1 2
D7202
LED
1 2
C723439PF
C7209100NF
C72004.7UF
C721410uF
R7202 4.7K/NC*
TISP4350H3BJR_S
D7200
1 2
C7208100NF
C72266PF/NC*
R7204
4.7K
C7211100NF
R7207
510
R7205
75
R7223
4.7K
R7222 0/NC*
X7200
25MHZ
1
1
GND1
2
3
3
GND2
4
T7200
G24_0413ER
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
C7210100NF
C72014.7UF
C7221 1NF/NC*
R7206
510
C72316PF/NC*
R7213
4.7K
D7201
LED
1 2
LB7201
1 2
C7223
22PF
R7224
4.7K
R7225
4.7K
LB7202
1 2
C72244.7uF
C720210uF
C720710uF
C72366PF/NC*
R7211
22
LB7200
1 2
C723539PF
C72276PF/NC*
C723039PF
R7210
22
R7226
4.7K
R7217 4.7K/NC*
C72326PF/NC*
B563S-8830-U004
J7200
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
SHLD1
9
SHLD2
10
M1
11
M2
12
R7209
22
R7215
22
C7206100NF
C72286PF/NC*
R7203
1.5K
C7204100NF
C7215100NF
C7220 1NF/NC*
C72031NF
MX2+
MX2+
MX2-
MX2-
TXDLY
TXDLY
RGMII_TXD1/SFC_EMMC_BOOT_MODE
RGMII_RXDV
EPHY_RSTN
$25N3685
$25N3684
$25N3720
$25N3643
$25N3645
$25N3644
MX1+
MX1+
RGMII_TXEN/BOOT_PAR_SEL3
MX1-
MX1-
$25N3719
$25N3718
MDIP3
MDIP3
MDIP2
MDIP2
PLLOFF
PLLOFF
RGMII_TXD3
MDIP1
MDIP1
RGMII_TXD2
AVDD_3V3_PHY
AVDD_3V3_PHY
MDIP0
MDIP0
$25N3712
REG_OUT_1.0V
REG_OUT_1.0V
REG_OUT_1.0V
REG_OUT_1.0V
REG_OUT_1.0V
LED2_1000M/CFG_LDO1
LED2_1000M/CFG_LDO1
LED2_1000M/CFG_LDO1
$25N3676
$25N3709
MX0+
MX0+
$25N3708
$25N3707
MX0-
MX0-
RGMII_TXCKOUT
LED1_100M/CFG_LDO0
LED1_100M/CFG_LDO0
LED1_100M/CFG_LDO0
$25N3702
EPHY_CLK/BOOT_PAR_SEL1
MDIO
$25N3703
ETH_XTALOUT
RGMII_RXCK
MX3-
MX3-
RXDLY
RXDLY
MX3+
MX3+
MDIN1
MDIN1
MDCK/BOOT_PAR_SEL2
MDIN0
MDIN0
RGMII_RXD3
MDIN3
MDIN3
MDIN2
MDIN2
RGMII_RXD0
PHY_AD0
PHY_AD0
RGMII_RXD2
RGMII_RXD1
PHY_AD2
PHY_AD2
LED0_10M/CFG_EXT
LED0_10M/CFG_EXT
PHY_AD1
PHY_AD1
VDDREG_3.3V
VDDREG_3.3V
RGMII_TXD0/BOOT_SEL1
ETH_XTALIN
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