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Document Revision History
Revision
Date
Author
Description
1.0
2019-05-01
CH Huang
First official release
1.1
2019-08-19
CH Huang
Updated 5.12 Thermal Controller.
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Table of Contents
Document Revision History .............................................................................................................................. 2
Table of Contents............................................................................................................................................. 3
1 System Overview ................................................................................................................................. 10
1.1 Highlighted Features Integrated in MT6785 ................................................................................... 10
1.2 Platform Features ............................................................................................................................ 12
1.3 Modem Features ............................................................................................................................. 14
1.4 Connectivity Features ...................................................................................................................... 16
1.5 Multimedia Features ....................................................................................................................... 18
2 Product Description ............................................................................................................................. 20
2.1 Pin Description ................................................................................................................................ 20
2.2 Electrical Characteristics ................................................................................................................. 39
2.3 System Configuration ...................................................................................................................... 60
2.4 Power-on Sequence ........................................................................................................................ 61
2.5 Analog Baseband ............................................................................................................................. 62
2.6 Package Information ....................................................................................................................... 69
3 MCU and Bus Fabric ............................................................................................................................. 71
3.1 MCU System .................................................................................................................................... 71
3.2 On-chip Memory Controller ............................................................................................................ 85
3.3 External Interrupt Controller (EINTC) .............................................................................................. 88
3.4 System Interrupt Controller (SYS_CIRQ) ......................................................................................... 95
3.5 Infrastructure System Configuration Module (INFRACFG) .............................................................. 98
3.6 External Memory Interface (EMI).................................................................................................. 100
3.7 DRAM Controller ........................................................................................................................... 102
3.8 AP_DMA ........................................................................................................................................ 107
3.9 CQ_DMA ........................................................................................................................................ 111
3.10 System Companion Processor (SCP) .............................................................................................. 114
3.11 System Timer (sys_timer) .............................................................................................................. 116
4 Clock and Power Control ................................................................................................................... 119
4.1 Top Clock Generator (TOPCKGEN) ................................................................................................ 119
4.2 Top Reset Generation Unit (TOPRGU)........................................................................................... 131
4.3 Frequency Hopping Controller (FHCTL) ......................................................................................... 134
5 Peripherals ........................................................................................................................................ 136
5.1 Pericfg Controller .......................................................................................................................... 136
5.2 GPIO Control ................................................................................................................................. 138
5.3 Keypad Scanner ............................................................................................................................. 139
5.4 UART .............................................................................................................................................. 143
5.5 Super Speed Universal Serial Bus (SSUSB) .................................................................................... 146
5.6 SPI Interface Controller ................................................................................................................. 149
5.7 MSDC Controller ............................................................................................................................ 153
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5.8 AUXADC ......................................................................................................................................... 168
5.9 I2C/I3C Controller .......................................................................................................................... 172
5.10 Pulse-Width Modulator (PWM) .................................................................................................... 183
5.11 General-Purpose Timer (GPT) ....................................................................................................... 185
5.12 Thermal Controller ........................................................................................................................ 187
5.13 Audio System ................................................................................................................................. 195
5.14 Universal Flash Storage (UFS) ........................................................................................................ 198
5.15 Bluetooth Interface (BTIF) ............................................................................................................. 200
6 Multimedia ........................................................................................................................................ 203
6.1 Display Controller .......................................................................................................................... 203
6.2 ISP .................................................................................................................................................. 206
6.3 Camera Serial Interface (CSI) ......................................................................................................... 207
6.4 AI Engine 1.0 (AIE1.0) .................................................................................................................... 210
6.5 AI Processor Unit System (APUSYS)............................................................................................... 213
6.6 Display PWM Generator ................................................................................................................ 215
6.7 Display Serial Interface (DSI) ......................................................................................................... 216
6.8 Digital Parallel Interface (DPI) ....................................................................................................... 218
6.9 Video Decoder (VDEC) ................................................................................................................... 221
6.10 H.264/HEVC Video Encoder .......................................................................................................... 223
6.11 MFG ............................................................................................................................................... 226
6.12 Modem Temperature Share (MODEM_TEMP_SHARE) ................................................................. 228
Exhibit 1 Terms and Conditions .................................................................................................................... 233
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Lists of Figures
Figure 1-1. High-level MT6785 functional block diagram ..................................................................................... 11
Figure 2-1. LPDDR4 ball map view ........................................................................................................................ 20
Figure 2-2. I2S master mode timing diagram ........................................................................................................ 44
Figure 2-3. LPDDR4X VIX definition ...................................................................................................................... 46
Figure 2-4. LPDDR4X single-ended output slew-rate definition ........................................................................... 46
Figure 2-5. LPDDR4X differential output slew-rate definition .............................................................................. 47
Figure 2-6. LPDDR4X Rx mask ............................................................................................................................... 47
Figure 2-7. SPI timing diagram .............................................................................................................................. 48
Figure 2-8. I2S master mode timing diagram ........................................................................................................ 48
Figure 2-9. I2C timing diagram of standard mode (100 kHz) and fast mode (400 kHz) ........................................ 49
Figure 2-10. MSDC device input timing diagram of default speed ....................................................................... 50
Figure 2-11. MSDC device output timing diagram of default speed ..................................................................... 50
Figure 2-12. MSDC device input timing diagram of high speed ............................................................................ 51
Figure 2-13. MSDC device output timing diagram of high speed ......................................................................... 51
Figure 2-14. MSDC device clock timing diagram of SDR12/SDR25/SDR50/SDR104 mode ................................... 52
Figure 2-15. MSDC device input timing diagram of SDR50/SDR104 mode .......................................................... 52
Figure 2-16. MSDC device output timing diagram of fixed data window (SDR12/SDR25/SDR50) ....................... 53
Figure 2-17. MSDC device output timing diagram of variable window (SDR104) ................................................ 53
Figure 2-18. MSDC device clock timing diagram of DDR50 speed mode .............................................................. 54
Figure 2-19. MSDC device input/output timing diagram of DDR50 speed mode ................................................. 54
Figure 2-20. MSDC device clock timing diagram of HS200 ................................................................................... 55
Figure 2-21. MSDC device input timing diagram of HS200 ................................................................................... 55
Figure 2-22. MSDC device output timing diagram of HS200 ................................................................................ 56
Figure 2-23. MSDC device input timing diagram of HS400 ................................................................................... 57
Figure 2-24. MSDC device output timing diagram of HS400 ................................................................................ 57
Figure 2-25. Block diagram of BBRX-ADC .............................................................................................................. 63
Figure 2-26. Block diagram of BBTX ...................................................................................................................... 64
Figure 2-27. Block diagram of ETDAC.................................................................................................................... 64
Figure 2-28. Block diagram of DETADC ................................................................................................................. 65
Figure 2-29. Block diagram of APC-DAC ................................................................................................................ 66
Figure 2-30. Outlines and dimensions of VFBGA 12.2 mm*12.2 mm, 779-ball, 0.9 mm package ........................ 69
Figure 2-31. Top marking of MT6785 .................................................................................................................... 69
Figure 3-1. Block diagram of on-chip memory controller ..................................................................................... 85
Figure 3-2. Security memory protection scheme ................................................................................................. 87
Figure 3-3. Block diagram of external interrupt controller ................................................................................... 89
Figure 3-4. Secure view of external interrupt controller ...................................................................................... 89
Figure 3-5. System level block diagram of system interrupt controller ................................................................ 95
Figure 3-6. Block diagram of system interrupt controller ..................................................................................... 96
Figure 3-7. DCM in action ..................................................................................................................................... 99
Figure 3-8. EMI/DRAM controller top connection (LP4) ..................................................................................... 101
Figure 3-9. Block diagram of DRAM controller ................................................................................................... 105
Figure 3-10. Example of scenario source wrap ................................................................................................... 113
Figure 3-11. Block diagram of SCP ...................................................................................................................... 115
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