IA-32 Intel
®
Architecture
Software Developer’s
Manual
Volume 2:
Instruction Set Reference
NOTE: The IA-32 Intel Architecture Software Developer’s Manual
consists of three volumes: Basic Architecture, Order Number 245470;
Instruction Set Reference, Order Number 245471; and the System
Programming Guide, Order Number 245472.
Please refer to all three volumes when evaluating your design needs.
2001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or
“undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
Intel’s IA-32 Intel
®
Architecture processors (e.g., Pentium
®
4 and Pentium
®
III processors) may contain design
defects or errors known as errata. Current characterized errata are available on request.
Intel
®
, Intel386™, Intel486™, Pentium
®
, Intel
®
Xeon™, Intel
®
NetBurst™, MMX™, and Itanium™ are trademarks
owned by Intel Corporation.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
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COPYRIGHT © 1997 - 2001 INTEL CORPORATION
iii
TABLE OF CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1. IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2. OVERVIEW OF THE IA-32 INTEL
®
ARCHITECTURE SOFTWARE
DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCE . . . . . 1-1
1.3. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE SOFTWARE
DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE . . . . . . . . . . . . . 1-2
1.4. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE SOFTWARE
DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE . . . . . 1-4
1.5. NOTATIONAL CONVENTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5.1. Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.5.2. Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.5.3. Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.4. Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.5.5. Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.5.6. Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.6. RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
CHAPTER 2
INSTRUCTION FORMAT
2.1. GENERAL INSTRUCTION FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2. INSTRUCTION PREFIXES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3. OPCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4. MODR/M AND SIB BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5. DISPLACEMENT AND IMMEDIATE BYTES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.6. ADDRESSING-MODE ENCODING OF MODR/M AND SIB BYTES. . . . . . . . . . . . 2-4
CHAPTER 3
INSTRUCTION SET REFERENCE
3.1. INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . 3-1
3.1.1. Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1.1.1. Opcode Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1.1.2. Instruction Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.1.1.3. Description Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.1.1.4. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.1.2. Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.1.3. Intel C/C++ Compiler Intrinsics Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.1.3.1. The Intrinsics API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.3.2. MMX™ Technology Intrinsics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.3.3. SSE and SSE2 Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.4. Flags Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
3.1.5. FPU Flags Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
3.1.6. Protected Mode Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
3.1.7. Real-Address Mode Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.1.8. Virtual-8086 Mode Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.1.9. Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.1.10. SIMD Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.2. INSTRUCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
TABLE OF CONTENTS
iv
PAGE
AAA—ASCII Adjust After Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
AAD—ASCII Adjust AX Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18
ADC—Add with Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
ADD—Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21
ADDPD—Add Packed Double-Precision Floating-Point Values . . . . . . . . . . . . .3-23
ADDPS—Add Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . .3-25
ADDSD—Add Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . .3-27
ADDSS—Add Scalar Single-Precision Floating-Point Values. . . . . . . . . . . . . . .3-29
AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31
ANDPD—Bitwise Logical AND of Packed Double-Precision
Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33
ANDPS—Bitwise Logical AND of Packed Single-Precision
Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35
ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision
Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-37
ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision
Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-39
ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . .3-41
BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . .3-43
BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45
BSR—Bit Scan Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-47
BSWAP—Byte Swap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49
BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-50
BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-52
BTR—Bit Test and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54
BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-56
CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-58
CBW/CWDE—Convert Byte to Word/Convert Word to Doubleword. . . . . . . . . .3-69
CDQ—Convert Double to Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70
CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71
CLD—Clear Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72
CLFLUSH—Flush Cache Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73
CLI—Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75
CLTS—Clear Task-Switched Flag in CR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-77
CMC—Complement Carry Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-78
CMOVcc—Conditional Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-79
CMP—Compare Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-83
CMPPD—Compare Packed Double-Precision Floating-Point Values. . . . . . . . .3-85
CMPPS—Compare Packed Single-Precision Floating-Point Values . . . . . . . . .3-89
CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands . . . . . . . . . . . . .3-93
CMPSD—Compare Scalar Double-Precision Floating-Point Values . . . . . . . . .3-96
CMPSS—Compare Scalar Single-Precision Floating-Point Values . . . . . . . . .3-100
CMPXCHG—Compare and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-104
CMPXCHG8B—Compare and Exchange 8 Bytes . . . . . . . . . . . . . . . . . . . . . .3-106
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TABLE OF CONTENTS
PAGE
COMISD—Compare Scalar Ordered Double-Precision Floating-Point
Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108
COMISS—Compare Scalar Ordered Single-Precision
Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . 3-111
CPUID—CPU Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114
CVTDQ2PD—Convert Packed Doubleword Integers to Packed
Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . 3-128
CVTDQ2PS—Convert Packed Doubleword Integers to Packed
Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . 3-130
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values
to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132
CVTPD2PI—Convert Packed Double-Precision Floating-Point Values
to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134
CVTPD2PS—Covert Packed Double-Precision Floating-Point Values
to Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . 3-136
CVTPI2PD—Convert Packed Doubleword Integers to Packed
Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . 3-138
CVTPI2PS—Convert Packed Doubleword Integers to Packed
Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . 3-140
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values
to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-142
CVTPS2PD—Covert Packed Single-Precision Floating-Point Values
to Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . 3-144
CVTPS2PI—Convert Packed Single-Precision Floating-Point Values
to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-146
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value
to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value
to Scalar Single-Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . 3-150
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision
Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision
Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value
to Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . 3-156
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value
to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158
CVTTPD2PI—Convert with Truncation Packed Double-Precision
Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . 3-160
CVTTPD2DQ—Convert with Truncation Packed Double-Precision
Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . 3-162
CVTTPS2DQ—Convert with Truncation Packed Single-Precision
Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . 3-164
CVTTPS2PI—Convert with Truncation Packed Single-Precision
Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . 3-166
CVTTSD2SI—Convert with Truncation Scalar Double-Precision
Floating-Point Value to Signed Doubleword Integer . . . . . . . . . . . . . . . 3-168
