P3U2A Interfaces to External Signals and Devices 第三部分第二单元课文A 外部信号与设备接口
4. 难句翻译
[1] In this interface, there is a “tristate” buffer which
when it is enabled will force the processor bus to
have the same binary value as the external data
lines.
在这种接口中,有一种三态缓冲器,它能迫使处理
器总线与外部数据线有相似二进制值。
[2] Ui is then removed and a known negative constant
reference voltage U is integrated which produces a
ramp down.
然后去掉Ui,对一种已知负常数参照电压U积分以
产生一种下降斜坡。
5. 参照译文
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