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TOSHIBA-TC51WKM616AXBN75.pdf
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TOSHIBA-TC51WKM616AXBN75.pdf
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TC51WKM616AXBN75
2002-08-22 1/11
• Access Times:
Access Time 75 ns
CE1 Access Time 75 ns
OE
Access Time 25 ns
Page Access Time 30 ns
• Package:
P-TFBGA48-0811-0.75BZ (Weight: g typ.)
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4,194,304-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM616AXBN is a 67,108,864-bit pseudo static random access memory(PSRAM) organized as
4,194,304 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.3 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by
CE1,OE, and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
FEATURES
• Organized as 4,194,304 words by 16 bits
• Dual power supplies(2.6 to 3.3 V for core and
1.7 to 2.2 V for output buffer)
• Direct TTL compatibility for all inputs and outputs
• Deep power-down mode: Memory cell data invalid
• Page operation mode:
Page read operation by 8 words
• Logic compatible with SRAM R/W (
WE ) pin
• Standby current
Standby 100 µA
Deep power-down standby 5 µA
PIN ASSIGNMENT
(TOP VIEW)
PIN NAMES
1 2 3 4 5 6
A
LB OE A0 A1 A2 CE2
B I/O9 UB A3 A4 CE1 I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D V
SS
I/O12 A17 A7 I/O4 V
DD
E V
DDQ
I/O13 A21 A16 I/O5 V
SS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 A19 A12 A13 WE I/O8
H A18 A8 A9 A10 A11 A20
(FBGA48)
A0 to A21 Address Inputs
A0 to A2 Page Address Inputs
I/O1 to I/O16 Data Inputs/Outputs
CE1
Chip Enable Input
CE2 Chip select Input
WE Write Enable Input
OE Output Enable Input
LB , UB Data Byte Control Inputs
V
DD
Power Supply for Core
V
DDQ
Power Supply for Output Buffer
GND Ground
TC51WKM616AXBN75
2002-08-22 2/11
BLOCK DIAGRAM
OPERATION MODE
MODE CE1 CE2 OE WE LB UB Add I/O1 to I/O8 I/O9 to I/O16 POWER
Read(Word) L H L H L L X D
OUT
D
OUT
I
DDO
Read(Lower Byte) L H L H L H X D
OUT
High-Z I
DDO
Read(Upper Byte) L H L H H L X High-Z D
OUT
I
DDO
Write(Word) L H X L L L X D
IN
D
IN
I
DDO
Write(Lower Byte) L H X L L H X D
IN
Invalid I
DDO
Write(Upper Byte) L H X L H L X Invalid D
IN
I
DDO
Outputs Disabled L H H H X X X High-Z High-Z I
DDO
Standby H H X X X X X High-Z High-Z I
DDS
Deep Power-down Standby H L X X X X X High-Z High-Z I
DDSD
Notes: L = Low-level Input(V
IL
), H = High-level Input(V
IH
), X = V
IH
or V
IL
, High-Z = High-impedance
V
DD
GND
I/O1
CE
I/O8
CE
I/O9
I/O16
OE
UB
LB
A0 A1 A2 A3 A4 A5
CE2
MEMORY CELL ARRAY
8,192
× 512 × 16
(67,108,864)
CONTROL SIGNAL
GENERATOR
SENSE AMP
A6
DATA OUTPUT
BUFFER
DATA OUTPUT
BUFFER
DATA INPUT
BUFFER
DATA INPUT
BUFFER
CE
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ROW ADDRESS BUFFER
COLUMN ADDRESS
DECODER
ROW ADDRESS
DECODER
COLUMN ADDRESS
BUFFER
I/O2
I/O3
I/O5
I/O4
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
A7 A8
REFRESH
CONTROL
REFRESH
ADDRESS
COUNTER
WE
CE1
A20
A21
TC51WKM616AXBN75
2002-08-22 3/11
ABSOLUTE MAXIMUM RATINGS (See Note 1)
SYMBOL RATING VALUE UNIT
V
DD
Power Supply Voltage −1.0 to 3.6 V
V
DDQ
Output Buffer Power Supply Voltage −1.0 to V
DD
+ 0.5 (3.6 V Max) V
V
IN
Input Voltage for Address and Control Pins −1.0 to 3.6 V
V
I/O
Input/Output Voltage for I/O Pins −1.0 to V
DDQ
+ 0.5 V
T
opr.
Operating Temperature −25 to 85 °C
T
strg.
Storage Temperature −55 to 150 °C
T
solder
Soldering Temperature (10 s) 260 °C
P
D
Power Dissipation 0.6 W
I
OUT
Short Circuit Output Current 50 mA
DC RECOMMENDED OPERATING CONDITIONS
(Ta
=
−
25°C to 85°C)
SYMBOL PARAMETER MIN TYP. MAX UNIT
V
DD
Power Supply Voltage 2.6 2.75 3.3
V
DDQ
Output Buffer Power Supply Voltage 1.7 1.8 2.2
Input High Voltage for Address and Control Pins 1.6 V
DD
+ 0.3*
V
IH
Input High Voltage for I/O Pins 1.6
V
DDQ
+ 0.3*
V
IL
Input Low Voltage −0.3* 0.4
V
* : V
IH
(Max) V
DD
+1.0 V/ V
DDQ
+1.0 V with 10 ns pulse width
V
IL
(Min) -1.0 V with 10 ns pulse width
DC CHARACTERISTICS
(Ta
=
−
25°C to 85°C, V
DD
=
2.6 to 3.3 V, V
DDQ
=
1.7 to 2.2 V)
(See Note 3 to 4)
SYMBOL PARAMETER TEST CONDITION MIN TYP. MAX UNIT
I
IL
Input Leakage Current V
IN
= 0 V to V
DDQ
−1.0 +1.0 µA
I
LO
Output Leakage Current Output disable, V
OUT
= 0 V to V
DD
−1.0 +1.0 µA
V
OH
Output High Voltage I
OH
= − 100 µA V
DDQ
− 0.2 V
V
OL
Output Low Voltage I
OL
= 100 µA 0.2 V
I
DDO1
Operating Current
CE1
= V
IL
CE2 = V
IH
, I
OUT
= 0 mA
t
RC
= min 50 mA
I
DDO2
Page Access Operating Current
CE1 = V
IL
, CE2 = V
IH
,
Page add. cycling, I
OUT
= 0 mA
t
PC
= min 25 mA
I
DDS
Standby Current(MOS) CE1 = V
DD
− 0.2 V, CE2 = V
DD
− 0.2 V 70 µA
I
DDSD
Deep Power-down Standby Current CE2 = 0.2 V 5 µA
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
C
IN
Input Capacitance V
IN
= GND 10 pF
C
OUT
Output Capacitance V
OUT
= GND 10 pF
Note: This parameter is sampled periodically and is not 100% tested.
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