IP5326 寄存器说明文档
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IP5326 寄存器说明文档
1 I2C 协议
The i2c speed support 300Kbps.Support 8 bit address width and 8bit data width. Transmit and receive MSB
first. The default slave address is 0Xea。
I2C acts as slave and is controlled by the master. The SCK line of the I2C interface is driven by the master.
The SDA line could be pulled up to VCC by a 2.2Kohm resister and pulled
down by either the master or the slave.A typical WRITE sequence for writing 8bits data to a register is
shown in below figure. A start bit isgiven by the master, followed by the slave address, register address and
8-bit data. After each 8-bit address or data transfer, the IP5326 gives an ACK bit. The master stops writing by
sending a stop bit.
All 8 bits data must be written before the register is updated.
Example: Write 8bit data 0x5a to register 0x05, and the slave address is 0Xea
Note：Sack generated by Slave, Mack generated by Master, and Mnack is a NACK generated by Master
Figure1 I2C WRITE
A typical READ sequence is shown in below figure. First the master has to write the slave address,followed
by the register address. Then a restart bit and the slave address specify that a READ is generated. The master
then clocks out 8 bits at a time to read data.
Example: Read 8bit data 0x5A from register 0x05, and the slave address is 0Xea
Figure2 I2C Read
SCLK
SDA
Start
sACK
Slave address 0xEA
sACK
Register address 0x05
sACK
Data 0x5A
Stop
SCLK
SDA
Start
sACK
Slave address 0xEA
sACK
Register address 0x05
mNACK
Data 0x5A
Stop
Restart
sACK
Slave address 0xEB
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