Serial ATA AHCI 1.3 Specification
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2.4.2 Offset SATACAP + 4h: SATACR1 – Serial ATA Capability Register 1 ................................................12
2.5 Other Capability Pointers.............................................................................................................. 13
3 HBA MEMORY REGISTERS ........................................................................................... 14
3.1 Generic Host Control .................................................................................................................... 14
3.1.1 Offset 00h: CAP – HBA Capabilities.....................................................................................................14
3.1.2 Offset 04h: GHC – Global HBA Control................................................................................................16
3.1.3 Offset 08h: IS – Interrupt Status Register.............................................................................................17
3.1.4 Offset 0Ch: PI – Ports Implemented.....................................................................................................17
3.1.5 Offset 10h: VS – AHCI Version ............................................................................................................18
3.1.6 Offset 14h: CCC_CTL – Command Completion Coalescing Control....................................................18
3.1.7 Offset 18h: CCC_PORTS – Command Completion Coalescing Ports .................................................19
3.1.8 Offset 1Ch: EM_LOC – Enclosure Management Location ...................................................................19
3.1.9 Offset 20h: EM_CTL – Enclosure Management Control ......................................................................19
3.1.10 Offset 24h: CAP2 – HBA Capabilities Extended...................................................................................20
3.1.11 Offset 28h: BOHC – BIOS/OS Handoff Control and Status..................................................................20
3.2 Vendor Specific Registers ............................................................................................................ 21
3.3 Port Registers (one set per port) .................................................................................................. 21
3.3.1 Offset 00h: PxCLB – Port x Command List Base Address...................................................................21
3.3.2 Offset 04h: PxCLBU – Port x Command List Base Address Upper 32-bits..........................................21
3.3.3 Offset 08h: PxFB – Port x FIS Base Address.......................................................................................22
3.3.4 Offset 0Ch: PxFBU – Port x FIS Base Address Upper 32-bits .............................................................22
3.3.5 Offset 10h: PxIS – Port x Interrupt Status ............................................................................................22
3.3.6 Offset 14h: PxIE – Port x Interrupt Enable ...........................................................................................23
3.3.7 Offset 18h: PxCMD – Port x Command and Status..............................................................................25
3.3.8 Offset 20h: PxTFD – Port x Task File Data ..........................................................................................27
3.3.9 Offset 24h: PxSIG – Port x Signature...................................................................................................27
3.3.10 Offset 28h: PxSSTS – Port x Serial ATA Status (SCR0: SStatus) .......................................................28
3.3.11 Offset 2Ch: PxSCTL – Port x Serial ATA Control (SCR2: SControl) ....................................................28
3.3.12 Offset 30h: PxSERR – Port x Serial ATA Error (SCR1: SError) ...........................................................30
3.3.13 Offset 34h: PxSACT – Port x Serial ATA Active (SCR3: SActive)........................................................31
3.3.14 Offset 38h: PxCI – Port x Command Issue...........................................................................................31
3.3.15 Offset 3Ch: PxSNTF – Port x Serial ATA Notification (SCR4: SNotification)........................................32
3.3.16 Offset 40h: PxFBS: Port x FIS-based Switching Control......................................................................32
3.3.17 Offset 70h to 7Fh: PxVS – Vendor Specific..........................................................................................32
4 SYSTEM MEMORY STRUCTURES .................................................................................... 33
4.1 HBA Memory Space Usage.......................................................................................................... 33
4.2 Port Memory Usage...................................................................................................................... 34
4.2.1 Received FIS Structure ........................................................................................................................35
4.2.2 Command List Structure.......................................................................................................................36
4.2.3 Command Table...................................................................................................................................39
5 DATA TRANSFER OPERATION ........................................................................................ 41
5.1 Introduction ................................................................................................................................... 41
5.2 HBA Controller State Machine (Normative).................................................................................. 41
5.2.1 Variables ..............................................................................................................................................41
5.2.2 HBA Idle States....................................................................................................................................41
5.3 HBA Port State Machine (Normative)........................................................................................... 43
5.3.1 Variables ..............................................................................................................................................43
5.3.2 Port Idle States.....................................................................................................................................45
5.3.3 FIS-based Switching Specific States....................................................................................................49
5.3.4 Power Management States..................................................................................................................50
5.3.5 Non-Data FIS Receive States ..............................................................................................................51
5.3.6 Command Transfer States ...................................................................................................................52
5.3.7 ATAPI Command Transfer States........................................................................................................54
5.3.8 D2H Register FIS Receive States ........................................................................................................54
5.3.9 PIO Setup Receive States....................................................................................................................56
5.3.10 Data Transmit States............................................................................................................................57
5.3.11 Data Receive States.............................................................................................................................58
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2008-10-30
14:12:41
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qqxlt2018-09-26收藏资料，还未来得及看
brianwen2013-09-04Good reference for SATA interface
