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AGM AG32 MCU用户手册
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AGM AG32 MCU用户手册,包含AG32VF103, AG32VF205,AG32VF303, AG32VF407等器件。
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AG32 MCU
Reference Manual
1.1
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contents
1 Device overview ________________________________________________________ 10
1.1 Introduction ______________________________________________________________ 10
1.1.1 _____________________________________________________________ 10
1.1.2 _____________________________________________ 10
1.1.3 Low- _________________________________________________________ 10
1.1.4 ADC/DAC/CMP/DMA/Timers/GPIO _________________________________________________ 10
1.1.5 _____________________________________________________ 11
1.1.6 Others ________________________________________________________________________ 11
1.2 Features and peripheral counts _______________________________________________ 12
1.3 Chip architecture __________________________________________________________ 13
1.4 Memory Map _____________________________________________________________ 14
1.5 System Control ____________________________________________________________ 14
2 Pin Definition __________________________________________________________ 22
3 Clock _________________________________________________________________ 28
3.1 Clock sources ______________________________________________________________ 28
3.2 HSE clock _________________________________________________________________ 29
3.3 HSI clock _________________________________________________________________ 30
3.4 PLL clock _________________________________________________________________ 31
3.5 LSE clock _________________________________________________________________ 31
3.6 LSI clock __________________________________________________________________ 31
3.7 System clock (SYSCLK) selection ______________________________________________ 31
3.8 RTC clock _________________________________________________________________ 31
3.9 Watchdog clock ____________________________________________________________ 32
4 Reset _________________________________________________________________ 33
4.1 System reset ______________________________________________________________ 33
4.2 Power reset _______________________________________________________________ 34
4.3 Backup domain reset _______________________________________________________ 34
5 Power control __________________________________________________________ 35
5.1 Power supplies ____________________________________________________________ 35
5.2 Independent ADC and DAC converter supply and reference voltage _________________ 35
5.3 Battery backup domain _____________________________________________________ 36
5.4 Voltage regulator __________________________________________________________ 36
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5.5 Power on reset (POR)/power down reset (PDR) _________________________________ 36
5.6 Low-power modes _________________________________________________________ 37
5.6.1 Slowing down system clocks ______________________________________________________ 37
5.6.2 Peripheral clock gating ___________________________________________________________ 37
5.6.3 Sleep mode ____________________________________________________________________ 37
5.6.4 Stop mode ____________________________________________________________________ 38
5.6.5 Standby mode__________________________________________________________________ 40
5.6.6 Auto-wakeup (AWU) from low-power mode __________________________________________ 41
6 Interrupt Controller _____________________________________________________ 42
6.1 Local interrupts ____________________________________________________________ 42
6.2 External interrupts _________________________________________________________ 42
6.3 Overall priority ____________________________________________________________ 44
6.4 Interrupt enable ___________________________________________________________ 44
6.5 Interrupt registers __________________________________________________________ 44
7 Dual Timer(Basic Timers) _________________________________________________ 46
7.1 Introduction ______________________________________________________________ 46
7.2 Functional Overview________________________________________________________ 47
7.2.1 Overview ______________________________________________________________________ 47
7.2.2 Functional description ___________________________________________________________ 48
7.3 Programmer’s Model _______________________________________________________ 55
7.3.1 ummary of registers _____________________________________________________________ 55
7.4 Register descriptions _______________________________________________________ 56
8 Advanced-control timers _________________________________________________ 60
8.1 Introduction ______________________________________________________________ 60
8.2 Main features _____________________________________________________________ 60
8.3 Functional description ______________________________________________________ 62
8.3.1 Time-base unit _________________________________________________________________ 62
8.3.2 Counter modes _________________________________________________________________ 64
8.3.3 Repetition counter ______________________________________________________________ 77
8.3.4 Clock selection _________________________________________________________________ 78
8.3.5 Capture/compare channels _______________________________________________________ 83
8.3.6 Input capture mode _____________________________________________________________ 87
8.3.7 PWM input mode _______________________________________________________________ 88
8.3.8 Forced output mode _____________________________________________________________ 89
8.3.9 Output compare mode ___________________________________________________________ 89
8.3.10 PWM mode _________________________________________________________________ 90
8.3.11 Complementary outputs and dead-time insertion ___________________________________ 95
8.3.12 Using the break function _______________________________________________________ 97
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8.3.13 Clearing the OCxREF signal on an external event ___________________________________ 100
8.3.14 6-step PWM generation _______________________________________________________ 101
8.3.15 One-pulse mode _____________________________________________________________ 101
8.3.16 Encoder interface mode _______________________________________________________ 103
8.3.17 Timer input XOR function ______________________________________________________ 106
8.3.18 Interfacing with Hall sensors ___________________________________________________ 106
8.3.19 External trigger synchronization ________________________________________________ 108
8.3.20 Timer synchronization ________________________________________________________ 112
8.3.21 Debug mode ________________________________________________________________ 112
8.4 registers _________________________________________________________________ 113
8.4.1 control register 1 (CR1) __________________________________________________________ 113
8.4.2 control register 2 (CR2) __________________________________________________________ 115
8.4.3 slave mode control register (SMCR) ________________________________________________ 117
8.4.4 DMA/interrupt enable register (DIER) ______________________________________________ 119
8.4.5 status register (SR) _____________________________________________________________ 121
8.4.6 event generation register (EGR) ___________________________________________________ 123
8.4.7 capture/compare mode register 1 (CCMR1) _________________________________________ 124
8.4.8 capture/compare mode register 2 (CCMR2) _________________________________________ 127
8.4.9 capture/compare enable register (CCER) ____________________________________________ 129
8.4.10 counter (CNT) _______________________________________________________________ 132
8.4.11 prescaler (PSC) ______________________________________________________________ 133
8.4.12 auto-reload register (ARR) _____________________________________________________ 133
8.4.13 repetition counter register (RCR) ________________________________________________ 133
8.4.14 capture/compare register 1 (CCR0) ______________________________________________ 134
8.4.15 capture/compare register 2 (CCR1) ______________________________________________ 135
8.4.16 capture/compare register 3 (CCR2) ______________________________________________ 135
8.4.17 capture/compare register 4 (CCR3) ______________________________________________ 136
8.4.18 break and dead-time register (BDTR) _____________________________________________ 136
8.4.19 register map ________________________________________________________________ 139
9 Watchdogs ___________________________________________________________ 141
9.1 Overview ________________________________________________________________ 141
9.2 Independent watchdog (IWDG) ______________________________________________ 141
9.2.1 IWDG main features ____________________________________________________________ 141
9.2.2 IWDG functional description _____________________________________________________ 141
9.2.3 Watchdog clock _______________________________________________________________ 142
9.2.4 Debug mode __________________________________________________________________ 142
9.2.5 IWDG registers ________________________________________________________________ 142
9.3 Functional overview _______________________________________________________ 144
9.3.1 Features _____________________________________________________________________ 144
9.3.2 Watchdog module overview _____________________________________________________ 144
9.3.3 Functional description __________________________________________________________ 145
9.3.4 Operation ____________________________________________________________________ 146
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9.3.5 Summary of registers ___________________________________________________________ 148
9.3.6 Register descriptions ___________________________________________________________ 149
10 Real-time clock (RTC) _________________________________________________ 152
10.1 RTC main features: ________________________________________________________ 152
10.2 RTC functional description __________________________________________________ 153
11 DMA ______________________________________________________________ 156
11.1 Overview ________________________________________________________________ 156
11.2 Functional Overview_______________________________________________________ 157
11.2.1 Functional description ________________________________________________________ 157
11.2.2 System considerations ________________________________________________________ 160
11.2.3 System connectivity __________________________________________________________ 161
11.2.4 Software considerations _______________________________________________________ 164
11.3 Programmer’s Model ______________________________________________________ 165
11.3.1 About the programmer’s model ________________________________________________ 165
11.3.2 Programming the DMAC ______________________________________________________ 166
11.3.3 Summary of registers _________________________________________________________ 167
11.3.4 Register descriptions _________________________________________________________ 172
11.3.5 Test registers ________________________________________________________________ 188
12 Analog-to-digital converter (ADC) _______________________________________ 191
12.1 Overview ________________________________________________________________ 191
12.2 Pins and internal signals ____________________________________________________ 191
12.3 Temperature sensor _______________________________________________________ 192
12.4 ADC block pins ___________________________________________________________ 192
12.5 ADC input signals vs package pins ____________________________________________ 194
12.6 ADC characteristics ________________________________________________________ 195
12.7 ADC timing diagram _______________________________________________________ 196
13 Digital-to-analog converter (DAC) _______________________________________ 197
13.1 Overview ________________________________________________________________ 197
13.2 DAC block pins ___________________________________________________________ 198
13.3 DAC pins ________________________________________________________________ 198
13.4 DACs output signals vs package pins __________________________________________ 198
13.5 DAC characteristics ________________________________________________________ 199
13.6 DAC output voltage _______________________________________________________ 199
14 Comparator (CMP) ___________________________________________________ 200
14.1 Overview ________________________________________________________________ 200
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