SPI接口主模式电路设计

附录一：约束脚本 read_verilog {dcspiiTop.v spii.v iospiipads.v} current_design dcspiiTop link check_design create_clock -name "clk" -period 20 [get_pins iospiipads/clk/C] set_clock_latency -max 0.5 [get_clocks clk] set_clock_transition -max 0.2 [get_clocks clk set_input_delay -max 12 -clock clk [get_pins "iospiipads/msb/C iospiipads/rd/C iospiipads/wr/C iospiipads/spidi/C iospiipads/statein*/C iospiipads/datain* /C"] set_output_delay -max 12 -clock clk [get_pins "iospiipads/spics/PAD iospiipads/spiclk/PAD iospiipads/spido/PAD iospiipads/dataout*/PAD "] set_dont_touch_network [get_clocks "clk"] set_ideal_network [get_ports "CLK"] set_dont_touch_network [get_ports RSTN] set_ideal_network [get_ports RSTN] check_timing set_operating_conditions -min fast -max slow -min_library fast -max_library slow set_wire_load_model -name tsmc18_wl20 -library slow set_load -min -pin_load 1 [get_ports "spics spido spiclk dataout*"] set_max_fanout 30 dcspiiTop set_drive 0.5 [get_ports "MSB RD WR SPIDI STATEIN* DATAIN* RSTN"] change_names -hierarchy -rules name_rule set verilogout_no_tri true set_fix_multiple_port_nets -all -buffer_constants compile -map high rc > ../output/tim.log write -f verilog -hier -o ../netlst/dc_top.sv write -f ddc -hier -o ../output/dc_top.ddc write_sdc ../output/dc_top.sdc report_area > ../output/top.area.log 附录二：管脚文件 Version: 1 Pad: iospiipads/CORNER1 SW Pad: iospiipads/CORNER2 SE Pad: iospiipads/CORNER3 NW Pad: iospiipads/CORNER4 NE Pad: iospiipads/datain_15 W Pad: iospiipads/datain_14 W Pad: iospiipads/datain_13 W Pad: iospiipads/datain_12 W Pad: iospiipads/datain_11 W Pad: iospiipads/datain_10 W Pad: iospiipads/datain_9 W Pad: iospiipads/datain_8 W Pad: iospiipads/datain_7 W Pad: iospiipads/datain_6 W Pad: iospiipads/datain_5 W Pad: iospiipads/datain_4 W Pad: iospiipads/datain_3 W Pad: iospiipads/datain_2 W Pad: iospiipads/datain_1 W Pad: iospiipads/datain_0 W Pad: iospiipads/dataout_15 E Pad: iospiipads/dataout_14 E Pad: iospiipads/dataout_13 E Pad: iospiipads/dataout_12 E Pad: iospiipads/dataout_11 E Pad: iospiipads/dataout_10 E Pad: iospiipads/dataout_9 E Pad: iospiipads/dataout_8 E Pad: iospiipads/dataout_7 E Pad: iospiipads/dataout_6 E Pad: iospiipads/dataout_5 E Pad: iospiipads/dataout_4 E Pad: iospiipads/dataout_3 E Pad: iospiipads/dataout_2 E Pad: iospiipads/dataout_1 E Pad: iospiipads/dataout_0 E Pad: iospiipads/clk S Pad: iospiipads/rstn S Pad: iospiipads/msb S Pad: iospiipads/spidi S Pad: iospiipads/rd S Pad: iospiipads/wr S Pad: iospiipads/vdd S Pad: iospiipads/vss S Pad: iospiipads/spido N Pad: iospiipads/spics N Pad: iospiipads/spiclk N Pad: iospiipads/vdd1 N Pad: iospiipads/vss1 N Pad: iospiipads/statein_2 N Pad: iospiipads/statein_1 N Pad: iospiipads/statein_0 N