Intel® PXA255 Processor
Developer’s Manual
March, 2003
Order Number: 278693-001
ii Intel® PXA255 Processor Developer’s Manual
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Intel® PXA255 Processor Developer’s Manual iii
Contents
Contents
1 Introduction...................................................................................................................................1-1
1.1 Intel® XScale™ Microarchitecture Features......................................................................1-1
1.2 System Integration Features..............................................................................................1-1
1.2.1 Memory Controller ................................................................................................1-2
1.2.2 Clocks and Power Controllers...............................................................................1-2
1.2.3 Universal Serial Bus (USB) Client.........................................................................1-2
1.2.4 DMA Controller (DMAC) .......................................................................................1-3
1.2.5 LCD Controller ......................................................................................................1-3
1.2.6 AC97 Controller ....................................................................................................1-3
1.2.7 Inter-IC Sound (I2S) Controller.............................................................................1-3
1.2.8 Multimedia Card (MMC) Controller.......................................................................1-3
1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-3
1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-4
1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4
1.2.12 GPIO.....................................................................................................................1-4
1.2.13 UARTs ..................................................................................................................1-4
1.2.14 Real-Time Clock (RTC).........................................................................................1-5
1.2.15 OS Timers.............................................................................................................1-5
1.2.16 Pulse-Width Modulator (PWM) .............................................................................1-5
1.2.17 Interrupt Control....................................................................................................1-5
1.2.18 Network Synchronous Serial Protocol Port...........................................................1-5
2 System Architecture .....................................................................................................................2-1
2.1 Overview............................................................................................................................2-1
2.2 Intel® XScale™ Microarchitecture Implementation Options..............................................2-2
2.2.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-2
2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3
2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3
2.2.4 Coprocessor 15 Register 0 - ID Register Definition..............................................2-3
2.2.5 Coprocessor 15 Register 1 - P-Bit ........................................................................2-4
2.3 I/O Ordering.......................................................................................................................2-5
2.4 Semaphores ......................................................................................................................2-5
2.5 Interrupts............................................................................................................................2-5
2.6 Reset .................................................................................................................................2-6
2.7 Internal Registers...............................................................................................................2-7
2.8 Selecting Peripherals vs. General Purpose I/O .................................................................2-7
2.9 Power on Reset and Boot Operation.................................................................................2-8
2.10 Power Management...........................................................................................................2-8
2.11 Pin List...............................................................................................................................2-8
2.12 Memory Map....................................................................................................................2-18
2.13 System Architecture Register Summary..........................................................................2-21
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Clock Manager Introduction...............................................................................................3-1
3.2 Power Manager Introduction..............................................................................................3-2
3.3 Clock Manager...................................................................................................................3-2
iv Intel® PXA255 Processor Developer’s Manual
Contents
3.3.1 32.768 kHz Oscillator............................................................................................3-4
3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4
3.3.3 Core Phase Locked Loop .....................................................................................3-4
3.3.4 95.85 MHz Peripheral Phase Locked Loop ..........................................................3-5
3.3.5 147.46 MHz Peripheral Phase Locked Loop ........................................................3-5
3.3.6 Clock Gating .........................................................................................................3-6
3.4 Resets and Power Modes..................................................................................................3-6
3.4.1 Hardware Reset....................................................................................................3-6
3.4.2 Watchdog Reset ...................................................................................................3-7
3.4.3 GPIO Reset ..........................................................................................................3-8
3.4.4 Run Mode .............................................................................................................3-9
3.4.5 Turbo Mode ..........................................................................................................3-9
3.4.6 Idle Mode............................................................................................................3-10
3.4.7 Frequency Change Sequence............................................................................3-11
3.4.8 33-MHz Idle Mode ..............................................................................................3-13
3.4.9 Sleep Mode.........................................................................................................3-15
3.4.10 Power Mode Summary .......................................................................................3-20
3.5 Power Manager Registers ...............................................................................................3-22
3.5.1 Power Manager Control Register (PMCR) .........................................................3-23
3.5.2 Power Manager General Configuration Register (PCFR)...................................3-24
3.5.3 Power Manager Wake-Up Enable Register (PWER)..........................................3-25
3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) ..........................3-26
3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER) ..........................3-27
3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR).............................3-28
3.5.7 Power Manager Sleep Status Register (PSSR) .................................................3-29
3.5.8 Power Manager Scratch Pad Register (PSPR) ..................................................3-30
3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)...............3-31
3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2).........3-31
3.5.11 Reset Controller Status Register (RCSR)...........................................................3-33
3.6 Clocks Manager Registers...............................................................................................3-34
3.6.1 Core Clock Configuration Register (CCCR) .......................................................3-34
3.6.2 Clock Enable Register (CKEN)...........................................................................3-36
3.6.3 Oscillator Configuration Register (OSCC) ..........................................................3-38
3.7 Coprocessor 14: Clock and Power Management ............................................................3-38
3.7.1 Core Clock Configuration Register (CCLKCFG).................................................3-39
3.7.2 Power Mode Register (PWRMODE)...................................................................3-40
3.8 External Hardware Considerations..................................................................................3-40
3.8.1 Power-On-Reset Considerations........................................................................3-40
3.8.2 Power Supply Connectivity.................................................................................3-40
3.8.3 Driving the Crystal Pins from an External Clock Source.....................................3-41
3.8.4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-41
3.9 Clocks and Power Manager Register Summary..............................................................3-41
3.9.1 Clocks Manager Register Locations...................................................................3-41
3.9.2 Power Manager Register Summary....................................................................3-41
4 System Integration Unit................................................................................................................4-1
4.1 General-Purpose I/O..........................................................................................................4-1
4.1.1 GPIO Operation....................................................................................................4-1
4.1.2 GPIO Alternate Functions.....................................................................................4-2
4.1.3 GPIO Register Definitions.....................................................................................4-6
Intel® PXA255 Processor Developer’s Manual v
Contents
4.2 Interrupt Controller...........................................................................................................4-20
4.2.1 Interrupt Controller Operation .............................................................................4-20
4.2.2 Interrupt Controller Register Definitions..............................................................4-21
4.3 Real-Time Clock (RTC) ...................................................................................................4-28
4.3.1 Real-Time Clock Operation.................................................................................4-28
4.3.2 RTC Register Definitions ....................................................................................4-29
4.3.3 Trim Procedure...................................................................................................4-32
4.4 Operating System (OS) Timer .........................................................................................4-34
4.4.1 Watchdog Timer Operation.................................................................................4-35
4.4.2 OS Timer Register Definitions ............................................................................4-35
4.5 Pulse Width Modulator.....................................................................................................4-38
4.5.1 Pulse Width Modulator Operation.......................................................................4-38
4.5.2 Register Descriptions..........................................................................................4-40
4.5.3 Pulse Width Modulator Output Wave Example...................................................4-43
4.6 System Integration Unit Register Summary.....................................................................4-44
4.6.1 GPIO Register Locations ....................................................................................4-44
4.6.2 Interrupt Controller Register Locations...............................................................4-45
4.6.3 Real-Time Clock Register Locations...................................................................4-45
4.6.4 OS Timer Register Locations..............................................................................4-45
4.6.5 Pulse Width Modulator Register Locations.........................................................4-46
5 DMA Controller.............................................................................................................................5-1
5.1 DMA Description................................................................................................................5-1
5.1.1 DMAC Channels ...................................................................................................5-2
5.1.2 Signal Descriptions...............................................................................................5-2
5.1.3 DMA Channel Priority Scheme .............................................................................5-3
5.1.4 DMA Descriptors...................................................................................................5-5
5.1.5 Channel States .....................................................................................................5-8
5.1.6 Read and Write Order...........................................................................................5-9
5.1.7 Byte Transfer Order..............................................................................................5-9
5.1.8 Trailing Bytes......................................................................................................5-10
5.2 Transferring Data.............................................................................................................5-11
5.2.1 Servicing Internal Peripherals.............................................................................5-11
5.2.2 Quick Reference for DMA Programming ............................................................5-13
5.2.3 Servicing Companion Chips and External Peripherals .......................................5-14
5.2.4 Memory-to-Memory Moves.................................................................................5-16
5.3 DMAC Registers ..............................................................................................................5-17
5.3.1 DMA Interrupt Register (DINT) ...........................................................................5-17
5.3.2 DMA Channel Control/Status Register (DCSRx)................................................5-17
5.3.3 DMA Request to Channel Map Registers (DRCMRx) ........................................5-20
5.3.4 DMA Descriptor Address Registers (DDADRx) ..................................................5-20
5.3.5 DMA Source Address Registers.........................................................................5-21
5.3.6 DMA Target Address Registers (DTADRx).........................................................5-22
5.3.7 DMA Command Registers (DCMDx)..................................................................5-23
5.4 Examples.........................................................................................................................5-26
5.5 DMA Controller Register Summary .................................................................................5-28
6 Memory Controller........................................................................................................................6-1
6.1 Overview............................................................................................................................6-1
6.2 Functional Description .......................................................................................................6-2
