基于i.MX6Q 四核Cortex-a9电视机顶盒 cadence ORCAD设计硬件（原理图+PCB+BOM）文件.zip

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eMMC

USB OTG/HOST

HDMI

LCD <LVDS IF>

SATA/PCIe/RGMII/LVDS

CONFIG

Audio Codec

SENSOR

SYS PWR

Charger

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Rev. Code Date DescriptionBy

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MAIN-IO CONNECTOR

PCIe

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MX6Q PWR

IOMUX

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PWR TREE

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VDD_CACHE

GND

GND

GND

GND

GND

GND

GND

GND

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G

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DRAM_A6

DRAM_A8

DRAM_A10

DRAM_A11

DRAM_A12

DRAM_A13

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_CS0_B

DRAM_RAS_B

DRAM_CAS_B

DRAM_WE_B

DRAM_DQM3

DRAM_DQM2

DRAM_A14

DRAM_A1

DRAM_A2

DRAM_A3

DRAM_A4

DRAM_A5

DRAM_A6

DRAM_A7

DRAM_A8

DRAM_A9

DRAM_A10

DRAM_A11

DRAM_SDBA1

DRAM_CS0_B

DRAM_CAS_B

DRAM_WE_B

DRAM_SDCLK0_B

DRAM_SDCKE0

DRAM_RESET_B

DRAM3_ZQ

DRAM_SDODT0

DRAM_DQM7

DRAM_DQM6

DRAM_A14DRAM_A14

DRAM_SDQS2

DRAM_SDQS3

DRAM_SDQS4

DRAM_SDQS5

DRAM_SDQS7

DRAM_DQM1

DRAM_DQM4

DRAM_DQM6

DRAM_SDQS0_B

DRAM_SDQS2_B

DRAM_SDQS7_B

DRAM_SDQS1

DRAM_SDQS1_B

DRAM_D20

DRAM_D18

DRAM_D19

DRAM_D27

DRAM_D31

DRAM_D22

DRAM_D17

DRAM_D23

DRAM_D21

DRAM_D53

DRAM_D55

DRAM_D58

DRAM_D54

DRAM_D51

DRAM_D62

DRAM_D63

DRAM_D56

DRAM_D48

DRAM_D60

DRAM_D57

DRAM_D59

DRAM_D61

GND GND

GND

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NOTE:

Using bit swapping for DATA bus to allow easy pcb routing.

When using data bit swapping the low order bit of each

byte must reside at bit 0 of the byte. The remaining 7 data

bits can be swapped freely. This restriction is for write

leveling calibration.

Example D0 to D0 or D0 to D8, and D1-7 can be swapped.

When swapping byte lanes on 16-bit memories, remember

C256

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C203

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10%

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10%

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MT41J256M16RE-15E:D

MT41J256M16RE-15E:D

10%

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10%

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C204

10%

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C204

10%

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C261

10uF/6.3V

10%

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C261

10uF/6.3V

10%

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C257

0.1uF/10V

10%

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C257

0.1uF/10V

10%

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C255

0.1uF/10V

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C255

0.1uF/10V

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R202

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1%

R202

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1%

10%

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10%

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R201

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10%

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10%

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0.1uF/10V

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0.1uF/10V

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10%

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10%

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C258

0.1uF/10V

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C258

0.1uF/10V

10%

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0.1uF/10V

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C262

0.1uF/10V

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10uF/6.3V

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C248

10uF/6.3V

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C249

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10%

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10%

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