Zynq开发-使用PYNQ快速入门摄像头MIPI驱动(OV5640)-overlay设计
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2024-05-12
21:42:57
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IIC_0
axi_iic_0
AXI IIC
S_AXI IIC
s_axi_aclk
s_axi_aresetn
iic2intc_irpt
gpo[0:0]
axi_intc_0
AXI Interrupt Controller
s_axi
interrupt
irq
s_axi_aclk
s_axi_aresetn
intr[2:0]
axi_vdma_0
AXI Video Direct Memory Access
S_AXI_LITE
M_AXI_S2MM
S_AXIS_S2MM
s_axi_lite_aclk
m_axi_s2mm_aclk
s_axis_s2mm_aclk
axi_resetn
s2mm_frame_ptr_in[5:0]
s2mm_frame_ptr_out[5:0]
s2mm_introut
axis_subset_converter_0
AXI4-Stream Subset Converter
S_AXIS
M_AXISaclk
aresetn
axis_subset_converter_1
AXI4-Stream Subset Converter
S_AXIS
M_AXISaclk
aresetn
clk_wiz_0
Clocking Wizard
clk_in1
clk_200m
locked
debug_bridge_0
Debug Bridge
S_AXI
s_axi_aclk
s_axi_aresetn
fan_en_b[0:0]
mipi_csi2_rx_subsyst_0
MIPI CSI-2 Rx Subsystem
mipi_phy_if
csirxss_s_axi
video_out
lite_aclk
lite_aresetn
dphy_clk_200M
rxbyteclkhs
clkoutphy_out
system_rst_out
pll_lock_out
csirxss_csi_irq
video_aclk
video_aresetn
mipi_phy_if_0
pixel_pack_0
Pixel Pack (Pre-Production)
s_axi_control
stream_in_24
stream_out_32
ap_clk
ap_rst_n
ps8_0_axi_periph
AXI Interconnect
S00_AXI
M00_AXI
M01_AXI
M02_AXI
M03_AXI
M04_AXI
M05_AXI
M06_AXI
ACLK
ARESETN
S00_ACLK
S00_ARESETN
M00_ACLK
M00_ARESETN
M01_ACLK
M01_ARESETN
M02_ACLK
M02_ARESETN
M03_ACLK
M03_ARESETN
M04_ACLK
M04_ARESETN
M05_ACLK
M05_ARESETN
M06_ACLK
M06_ARESETN
rpi_cam_en
rst_ps8_0_99M
Processor System Reset
slowest_sync_clk
ext_reset_in
aux_reset_in
mb_debug_sys_rst
dcm_locked
mb_reset
bus_struct_reset[0:0]
peripheral_reset[0:0]
interconnect_aresetn[0:0]
peripheral_aresetn[0:0]
system_ila_1
System ILA
SLOT_0_AXIS
clk
resetn
v_demosaic_0
Sensor Demosaic
s_axi_CTRL
s_axis_video m_axis_video
ap_clk
ap_rst_n
interrupt
xlconcat_0
Concat
In0[0:0]
In1[0:0]
In2[0:0]
dout[2:0]
xlslice_0
Slice
Din[2:0] Dout[0:0]
zynq_ultra_ps_e_0
Zynq UltraScale+ MPSoC
M_AXI_HPM0_FPD
S_AXI_HPC0_FPD GPIO_0
maxihpm0_fpd_aclk
saxihpc0_fpd_aclk
emio_ttc0_wave_o[2:0]
pl_ps_irq0[0:0]
pl_resetn0
pl_clk0
pl_clk1
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