+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
基于varilog语言在quartusii软件实现洗衣机控制程序
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2024-04-17
21:32:24
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基于varilog语言在quartusii软件实现洗衣机控制程序 （187个子文件） 
_info 1KB _info 1KB _vmake 26B _vmake 26B xiyiji.root_partition.cmp.ammdb 486B xiyiji.vpr.ammdb 457B xiyiji.map.ammdb 138B xiyiji.v.bak 8KB xiyiji_tb.v.bak 1KB xiyiji_run_msim_rtl_verilog.do.bak 547B xiyiji_run_msim_gate_verilog.do.bak 497B xiyiji_run_msim_rtl_verilog.do.bak1 547B xiyiji_run_msim_gate_verilog.do.bak1 497B xiyiji_run_msim_gate_verilog.do.bak10 497B xiyiji_run_msim_gate_verilog.do.bak11 497B xiyiji_run_msim_rtl_verilog.do.bak2 547B xiyiji_run_msim_gate_verilog.do.bak2 497B xiyiji_run_msim_rtl_verilog.do.bak3 547B xiyiji_run_msim_gate_verilog.do.bak3 497B xiyiji_run_msim_rtl_verilog.do.bak4 547B xiyiji_run_msim_gate_verilog.do.bak4 497B xiyiji_run_msim_rtl_verilog.do.bak5 547B xiyiji_run_msim_gate_verilog.do.bak5 497B xiyiji_run_msim_rtl_verilog.do.bak6 547B xiyiji_run_msim_gate_verilog.do.bak6 497B xiyiji_run_msim_rtl_verilog.do.bak7 547B xiyiji_run_msim_gate_verilog.do.bak7 497B xiyiji_run_msim_rtl_verilog.do.bak8 547B xiyiji_run_msim_gate_verilog.do.bak8 497B xiyiji_run_msim_rtl_verilog.do.bak9 547B xiyiji_run_msim_gate_verilog.do.bak9 497B xiyiji.cmp.bpm 819B xiyiji.map.bpm 789B xiyiji.cmp.cdb 34KB xiyiji.root_partition.cmp.cdb 15KB xiyiji.sgdiff.cdb 11KB xiyiji.map.cdb 11KB xiyiji.root_partition.map.cdb 10KB xiyiji.rtlv_sg.cdb 9KB xiyiji.(0).cnf.cdb 8KB xiyiji.(4).cnf.cdb 8KB xiyiji.map_bb.cdb 2KB xiyiji.root_partition.map.hbdb.cdb 1KB xiyiji.(3).cnf.cdb 1KB xiyiji.(1).cnf.cdb 1KB xiyiji.(7).cnf.cdb 1KB xiyiji.(6).cnf.cdb 1KB xiyiji.(8).cnf.cdb 1KB xiyiji.(2).cnf.cdb 1KB xiyiji.(5).cnf.cdb 932B xiyiji.root_partition.map.reg_db.cdb 553B xiyiji.rtlv_sg_swap.cdb 196B xiyiji_8_1200mv_85c_v_slow.sdo_typ.csd 22KB _primary.dat 96KB logic_util_heursitic.dat 14KB _primary.dat 3KB _primary.dat 875B _primary.dat 875B xiyiji.db_info 155B xiyiji.db_info 155B _primary.dbs 93KB _primary.dbs 3KB _primary.dbs 998B _primary.dbs 998B xiyiji.tiscmp.slow_1200mv_0c.ddb 186KB xiyiji.tiscmp.slow_1200mv_85c.ddb 186KB xiyiji.tiscmp.fast_1200mv_0c.ddb 185KB xiyiji.tiscmp.fastest_slow_1200mv_85c.ddb 127KB xiyiji.tiscmp.fastest_slow_1200mv_0c.ddb 127KB xiyiji.asm_labs.ddb 12KB xiyiji.tis_db_list.ddb 250B xiyiji.pti_db_list.ddb 192B xiyiji.root_partition.cmp.dfp 33B xiyiji_run_msim_rtl_verilog.do 547B xiyiji_run_msim_gate_verilog.do 497B xiyiji.done 26B xiyiji.root_partition.map.dpi 803B xiyiji.root_partition.map.hbdb.hb_info 46B xiyiji.sgdiff.hdb 20KB xiyiji.cmp.hdb 18KB xiyiji.root_partition.cmp.hdb 18KB xiyiji.map.hdb 18KB xiyiji.root_partition.map.hdb 18KB xiyiji.root_partition.map.hbdb.hdb 17KB xiyiji.pre_map.hdb 12KB xiyiji.rtlv.hdb 12KB xiyiji.map_bb.hdb 11KB xiyiji.(4).cnf.hdb 5KB xiyiji.(0).cnf.hdb 3KB xiyiji.(3).cnf.hdb 779B xiyiji.(6).cnf.hdb 679B xiyiji.(8).cnf.hdb 663B xiyiji.(2).cnf.hdb 663B xiyiji.(5).cnf.hdb 659B xiyiji.(1).cnf.hdb 602B xiyiji.(7).cnf.hdb 601B xiyiji.hier_info 3KB xiyiji.hif 1KB xiyiji.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd 729KB xiyiji.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd 723KB共 187 条
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