1916
IEEE
JOURNAL
OF
SOLID-STATE CIRCUITS.
VOL.
27.
NO.
12.
DECEMBER
1992
Design Techniques for High-speed, High-Resolution
Comparators
Behzad Razavi,
Member,
IEEE,
and Bruce
A.
Wooley,
Fellow,
IEEE
Abstract-This paper describes precision techniques for the
design of comparators used in high-performance analog-to-dig-
ita1 converters employing parallel conversion stages. Following
a review of conventional offset cancellation techniques, circuit
designs achieving 12-b resolution in both BiCMOS and CMOS
5-V
technologies are presented. The BiCMOS comparator con-
sists of a preamplifier followed by two regenerative stages and
achieves an offset of 200
pV
at a
IO-MHz
clock rate while dis-
sipating
1.7
mW. In the CMOS comparator offset cancellation
is used in both a single-stage preamplifier and a subsequent
latch to achieve an offset of less than
300
pV
at comparison
rates as high as
10
MHz,
with a power dissipation of
1.8
mW.
I.
INTRODUCTION
The next section of this paper reviews some of the con-
ventional approaches to offset cancellation and identifies
their fundamental trade-offs and limitations. The Bi-
CMOS comparator is then described in Section 111, and
the design of the CMOS comparator is presented in Sec-
tion IV. The experimental results obtained for both cir-
cuits are summarized in Section V.
11.
OFFSET
CANCELLATION
TECHNIQUES
A.
Circuit
Topologies
The analog sampling capability inherent in CMOS and
BiCMOS technologies provides a means whereby offsets
N
high-speed analog-to-digital converters, comparator
can
be
Periodical'Y sensed, stored,
and
then
subtracted
Idesign has a crucial influence
on
the overall
perfor-
from the input
incorporate a large number of comparators in parallel to
Offset
(Ios)
and
Output
Offset ('Os),
on the delay, resolution, power dissipation, input voltage two approaches
as
to
a
'Ompar-
range, input impedance, and area of those circuits. More-
comprises
a
preamplifier,
Of
the
various
Offset
mance that can be achieved. Converter architectures that
two
Of
the
most
''"On
approaches'
based
On
obtain
a
high throughput
rate
impose stringent
constraints
are considered herein. Fig. l(a> and (b) illustrates these
ator* Each
Of
these
over, the relatively large device mismatch and limited
offset storage capacitors, and a latch. With
IOS,
the can-
voltage range that accompany the integration of compar-
cellation is Performed
a
unitY-gain loop
around
ator circuits in low-voltage scaled VLSI technologies se-
verely compromise the precision that can be obtained.
This paper introduces a number
of
comparator design
techniques for use in parallel
A/D
converters that are im-
the preamplifier
and
storing
the
Offset On
the
input
piing
capacitors. With
Oos?
the
Offset
is
by
shorting the preamplifier inputs
and
storing
the
amp1ified
Offset
On the
Output
Of
capacitors*
A
plemented in BiCMOS and
CMOS
vLsI
technologies.
The suggested methods are intended to provide improved
resolution and speed while
maintaining
low
power
dissi-
pation, a small input capacitance, and low complexity.
The techniques are presented within the context of prac-
these two approaches reveals their respective merits and
In the comparator with IOS, the residual input-referred
Offset
(i.e.7
the Offset
after
is
(1)
vosi
AQ
VOX.
v,,
=
___
+-+-
tical designs for both a BiCMOS and a CMOS comparator
BiCMOS comparator employs a low-gain Preamplifier
followed by two regenerative amplifiers to achieve an
off-
set
Of
200
pv
at
'lock
as
high
as
lo
MHz.
In
the
CMOS comparator, ofiset cancellation is used in both the
preamplifier and the subsequent latch to achieve an offset
of less than
300
pV at 10 MHz.
with 12-b resolution at 10-MHz comparison rates. The 1
+
A0
C
A0
where
v,,,
and
A.
are the input offset and gain of the
preamplifier, respectively,
AQ
is the mismatch in charge
injection from switches
S5
and
S6
onto capacitors C1 and
c2, and
v,,
is the latch offset. In the comparator em-
ploying
oos,
the residual
offset
is
(2)
AQ
vox
v,,
=
-
+
-.
AoC
A0
Manuscript received March 4, 1992; revised July 13, 1992. This work
was supported by the Army Research Office under Contract DAAL03-91-
G-0088.
B. Razavi was with the Center for Integrated Systems, Stanford Univer-
Equations (l)
and
(2) show that,
for
similar preamplifiers,
sity, Stanford, CA 94305. He is now with AT&T Bell Laboratories, Holm-
del,
NJ
07733.
B. A. Wooley
is
with the Center
for
Integrated Systems, Stanford Uni-
versitv. Stanford. CA 94305.
the residual offset obtainable using
00s
can be Smaller
than that for
10s.
In fact, unless sufficient statistical data
for
V,,
AQ,
and
VosL
are available,
10s
requires the use
~~
IEEE Log
Number
9204 135.
of quite large values for
A.
and
C
to guarantee a low
Vas.
0018-9200/92$03.00
0
1992
IEEE
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