高速，高分辨率比较器的设计技术。资源-CSDN文库

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摘要:本文描述了用于采用并行转换级的高性能模数转换器的比较器设计的精密技术。在回顾了传统的偏移消除技术后，给出了在BiCMOS和CMOS 5-V工艺中实现12-b分辨率的电路设计。 BiCMOS比较器由一个前置放大器和两个再生级组成，在10Mhz时钟频率下实现200 uV的偏移，消耗1.7 mW。在CMOS比较器中，在单级前置放大器和后续锁存器中都使用了偏移消除，以在高达10 MHz的比较速率下实现小于300 uV的偏移，功耗为1.8 mW。 Razavi B, Wooley B A. Design techniques for high peed, high-resolution omparators [J]. IEEE J SlSta Circ, 1992, 27 (12) : 1916 1926 参考：https://blog.csdn.net/Carol0630/article/details/124839133?csdn_share_tail=%7B%22type%22%3A%22blog%22%2C%22rType%22%3A%22article%22%2C%22rId 【比较器设计技术】在高速、高分辨率的模拟到数字转换器（ADC）中，比较器扮演着至关重要的角色。本文“高速，高分辨率比较器的设计技术”深入探讨了用于高性能ADC的比较器设计的精确方法，特别是采用了并行转换级的ADC。作者Behzad Razavi和Bruce A. Wooley在1992年的IEEE Journal of Solid-State Circuits期刊中详细阐述了这一主题。文章回顾了传统的偏移消除技术。在比较器设计中，偏移是关键的性能指标，因为它直接影响到转换器的分辨率和精度。偏移分为输入偏移（Ios）和输出偏移（Oos），它们可能导致测量结果的误差。文章中提到的两种主要的偏移消除电路拓扑结构包括：一种是预放大器，另一种是再生级。这两种方法都有其独特的优点和局限性，需要权衡速度、分辨率、功耗和输入电压范围等因素。接下来，文章介绍了在BiCMOS（双极型互补金属氧化物半导体）和CMOS（互补金属氧化物半导体）5-V工艺中实现12位分辨率的比较器设计。BiCMOS比较器由预放大器和两个再生级组成，能在10MHz的时钟频率下工作，实现200微微伏（pV）的偏移，功耗仅为1.7毫瓦（mW）。这种设计体现了BiCMOS技术在高速度和高精度之间的良好平衡。相比之下，CMOS比较器则通过在单级预放大器和后续的锁存器中应用偏移消除技术，实现了在10MHz的比较速率下小于300 pV的偏移，功耗为1.8 mW。这种方法突显了CMOS技术在降低功耗和提高分辨率方面的潜力。文章的实验结果部分总结了这两个电路的实际表现，展示了设计策略在实际应用中的效果。这些设计技术对于开发高速、低偏移、低功耗的比较器至关重要，对于提升ADC的整体性能具有显著影响。该论文提供了关于如何在高速环境下优化比较器设计的关键见解，涵盖了从传统的偏移取消技术到具体BiCMOS和CMOS实现的详细讨论。这些技术对设计者来说是极其宝贵的，可以帮助他们克服在构建高精度模拟到数字转换系统时面临的挑战。

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1916

IEEE

JOURNAL

SOLID-STATE CIRCUITS.

VOL.

27.

NO.

12.

DECEMBER

1992

Design Techniques for High-speed, High-Resolution

Comparators

Behzad Razavi,

Member,

IEEE,

and Bruce

Wooley,

Fellow,

IEEE

Abstract-This paper describes precision techniques for the

design of comparators used in high-performance analog-to-dig-

ita1 converters employing parallel conversion stages. Following

a review of conventional offset cancellation techniques, circuit

designs achieving 12-b resolution in both BiCMOS and CMOS

5-V

technologies are presented. The BiCMOS comparator con-

sists of a preamplifier followed by two regenerative stages and

achieves an offset of 200

at a

IO-MHz

clock rate while dis-

sipating

1.7

mW. In the CMOS comparator offset cancellation

is used in both a single-stage preamplifier and a subsequent

latch to achieve an offset of less than

300

at comparison

rates as high as

MHz,

with a power dissipation of

1.8

mW.

INTRODUCTION

The next section of this paper reviews some of the con-

ventional approaches to offset cancellation and identifies

their fundamental trade-offs and limitations. The Bi-

CMOS comparator is then described in Section 111, and

the design of the CMOS comparator is presented in Sec-

tion IV. The experimental results obtained for both cir-

cuits are summarized in Section V.

11.

OFFSET

CANCELLATION

TECHNIQUES

Circuit

Topologies

The analog sampling capability inherent in CMOS and

BiCMOS technologies provides a means whereby offsets

high-speed analog-to-digital converters, comparator

can

Periodical'Y sensed, stored,

and

then

subtracted

Idesign has a crucial influence

the overall

perfor-

from the input

incorporate a large number of comparators in parallel to

Offset

(Ios)

and

Output

Offset ('Os),

on the delay, resolution, power dissipation, input voltage two approaches

'Ompar-

range, input impedance, and area of those circuits. More-

comprises

preamplifier,

the

various

Offset

mance that can be achieved. Converter architectures that

two

the

most

''"On

approaches'

based

obtain

high throughput

rate

impose stringent

constraints

are considered herein. Fig. l(a> and (b) illustrates these

ator* Each

these

over, the relatively large device mismatch and limited

offset storage capacitors, and a latch. With

IOS,

the can-

voltage range that accompany the integration of compar-

cellation is Performed

unitY-gain loop

around

ator circuits in low-voltage scaled VLSI technologies se-

verely compromise the precision that can be obtained.

This paper introduces a number

comparator design

techniques for use in parallel

A/D

converters that are im-

the preamplifier

and

storing

the

Offset On

the

input

piing

capacitors. With

Oos?

the

Offset

shorting the preamplifier inputs

and

storing

the

amp1ified

Offset

On the

Output

capacitors*

plemented in BiCMOS and

CMOS

vLsI

technologies.

The suggested methods are intended to provide improved

resolution and speed while

maintaining

low

power

dissi-

pation, a small input capacitance, and low complexity.

The techniques are presented within the context of prac-

these two approaches reveals their respective merits and

In the comparator with IOS, the residual input-referred

Offset

(i.e.7

the Offset

after

(1)

vosi

VOX.

v,,

___

+-+-

tical designs for both a BiCMOS and a CMOS comparator

BiCMOS comparator employs a low-gain Preamplifier

followed by two regenerative amplifiers to achieve an

off-

set

200

'lock

high

MHz.

the

CMOS comparator, ofiset cancellation is used in both the

preamplifier and the subsequent latch to achieve an offset

of less than

300

pV at 10 MHz.

with 12-b resolution at 10-MHz comparison rates. The 1

where

v,,,

and

are the input offset and gain of the

preamplifier, respectively,

is the mismatch in charge

injection from switches

and

onto capacitors C1 and

c2, and

v,,

is the latch offset. In the comparator em-

ploying

oos,

the residual

offset

(2)

vox

v,,

AoC

Manuscript received March 4, 1992; revised July 13, 1992. This work

was supported by the Army Research Office under Contract DAAL03-91-

G-0088.

B. Razavi was with the Center for Integrated Systems, Stanford Univer-

Equations (l)

and

(2) show that,

for

similar preamplifiers,

sity, Stanford, CA 94305. He is now with AT&T Bell Laboratories, Holm-

del,

07733.

B. A. Wooley

with the Center

for

Integrated Systems, Stanford Uni-

versitv. Stanford. CA 94305.

the residual offset obtainable using

00s

can be Smaller

than that for

10s.

In fact, unless sufficient statistical data

for

V,,

AQ,

and

VosL

are available,

10s

requires the use

IEEE Log

Number

9204 135.

of quite large values for

and

to guarantee a low

Vas.

0018-9200/92$03.00

1992

IEEE

Authorized licensed use limited to: Southeast University. Downloaded on August 14,2022 at 02:01:26 UTC from IEEE Xplore. Restrictions apply.

RAZAVI AND WOOLEY: DESIGN TECHNIQUES FOR HIGH-SPEED, HIGH-RESOLUTION COMPARATORS

1917

vi,

(b)

Fig.

Comparator offset cancellation techniques: (a) input offset storage,

and

(b)

output offset storage.

Since the value of the input coupling capacitors with

10s

is governed by charge injection,

kT/C

noise, and at-

tenuation considerations, the input capacitance of this to-

pology is usually higher than that of the

00s

configura-

tion. During offset cancellation, the input capacitance of

the

10s

circuit is equal to the offset storage capacitor,

while in the comparison mode it is approximately the sum

of the input capacitance of the preamplifier and the para-

sitic capacitances of the offset storage capacitor. These

parasitic capacitances are typically as large as

0.1

0.2

pF for input storage capacitors in the range of

0.5

pF, whereas the preamplifier input capacitance can be

maintained below

fF.

For this reason

00s

is generally

preferable in flash stages, where many comparators are

connected in parallel.

course, the dc coupling at the

input of an

00s

comparator limits the common-mode

range. Also, in applications where a large differential ref-

erence voltage must be stored in the comparator

[2],

the

preamplifier of the

00s

topology must be designed for a

low gain

that it does not saturate at its output.

While

10s

is accomplished by means of a closed feed-

back loop, which forces the preamplifier into its active

region,

00s

is normally an open-loop operation that re-

quires tight control of the amplifier gain. Therefore,

00s

is typically implemented using a single-stage amplifier

with a gain of less than

to ensure operation in the active

region under extreme variations in device matching and

supply voltage.

In conventional CMOS comparator designs, the pream-

plifier is typically followed by a standard dynamic CMOS

latch. As shown in the following subsection, this latch has

a potentially large input offset and therefore requires the

use of a high-gain preamplifier in order to achieve a low

offset. Consequently, in high-resolution applications a

single stage of

00s

cannot be used, while a single-stage

high-gain preamplifier with

10s

suffers from a long delay.

The above considerations have led to the use of multi-

stage calibration techniques in high-resolution applica-

Fig.

Multistage offset cancellation

tions. Fig.

illustrates a typical multistage comparator

topology that, in effect, utilizes both

10s

and

00s

when

it is clocked sequentially

[2],

[3].

The overall gain of the

circuit is chosen

that an input of

0.5

LSB

overcomes

the offset of the latch

(50

100

mV), and the number of

stages is then selected to provide the smallest delay

[2].

In the configuration of Fig.

a large latch offset

ac-

commodated through the use of multiple preamplifier

stages, each with offset cancellation. Alternatively, the

offset of the latch can be reduced

as to relax the gain

required of the preamplifier. This can be accomplished

through the use of either devices with inherently low

off-

sets or offset cancellation in the latch.

Design Constraints

a Dynamic CMOS htch

In order to synchronize the operation of a comparator

with other parts of a system, as well as provide the gain

needed to generate logic levels at the output, a regenera-

tive amplifier is normally used as the final comparator

stage. Fig.

shows a dynamic CMOS latch similar to that

used in

[4]

to amplify small differences to CMOS levels.

In this circuit, when

is low,

is off,

and

are

on, and the latch senses the inputs

Vjnl

and

Vjn2.

When

goes high,

and

turn off to isolate nodes

and

from input terminals and

turns on to initiate regen-

eration.

In order to simplify calculations and estimate a lower

bound for the offset of the latch in Fig.

only the mis-

matches between

and

and between

and

are

considered here. In practice, other errors such

mis-

matches between

and

further increase the offset.

Considering only the

M1,

and

S1,

mismatches,

the input offset

the latch can be expressed as

(3)

where

AV,,

and

V,,

are the standard deviation and mean

of the threshold voltage,

AW/W

and

U/L

are relative

dimension mismatches,

VGs

VTH

represents the initial

gate-source overdrive,

is the charge injection mis-

match between

and

S2,

and

the total capacitance

(assumed equal on both sides). For optimistic

values of

AVTH

mV,

AW/W

AL/L

0.05,

VGs

VTH

0.5

fC, and

100

fF,

the latch

offset voltage is approximately

mV, with its major

component arising from the second term in

(3).

This term

can be reduced by increasing

and

and/or decreasing

VGs

VTH,

i.e., decreasing the initial drain current of

and

M2.

However, these remedies can degrade the speed

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