Document Number: 001-98284 Rev. *Q Page 3 of 145
Contents
Features................................................................................. 1
Logic Block Diagram ............................................................ 1
Performance Summary ........................................................ 2
1. Overview ....................................................................... 4
1.1 General Description ....................................................... 4
1.2 Migration Notes.............................................................. 4
1.3 Glossary......................................................................... 7
1.4 Other Resources............................................................ 7
Hardware Interface
2. Signal Descriptions ..................................................... 8
2.1 Input/Output Summary................................................... 8
2.2 Address and Data Configuration.................................... 9
2.3 RESET# ......................................................................... 9
2.4 Serial Clock (SCK)......................................................... 9
2.5 Chip Select (CS#) .......................................................... 9
2.6 Serial Input (SI) / I/O0 .................................................. 10
2.7 Serial Output (SO) / I/O1.............................................. 10
2.8 Write Protect (WP#) / I/O2 ........................................... 10
2.9 Hold (HOLD#) / I/O3 .................................................... 10
2.10 Core Voltage Supply (V
CC
) .......................................... 11
2.11 Versatile I/O Power Supply (V
IO
) ................................. 11
2.12 Supply and Signal Ground (V
SS
) ................................. 11
2.13 Not Connected (NC) .................................................... 11
2.14 Reserved for Future Use (RFU)................................... 11
2.15 Do Not Use (DNU) ....................................................... 11
2.16 Block Diagrams............................................................ 12
3. Signal Protocols......................................................... 13
3.1 SPI Clock Modes ......................................................... 13
3.2 Command Protocol ...................................................... 14
3.3 Interface States............................................................ 17
3.4 Configuration Register Effects on the Interface ........... 22
3.5 Data Protection ............................................................ 22
4. Electrical Specifications............................................ 23
4.1 Absolute Maximum Ratings ......................................... 23
4.2 Thermal Resistance..................................................... 23
4.3 Operating Ranges........................................................ 23
4.4 Power-Up and Power-Down ........................................ 24
4.5 DC Characteristics....................................................... 26
5. Timing Specifications................................................ 27
5.1 Key to Switching Waveforms ....................................... 27
5.2 AC Test Conditions...................................................... 28
5.3 Reset............................................................................ 29
5.4 SDR AC Characteristics............................................... 31
5.5 DDR AC Characteristics .............................................. 35
6. Physical Interface ...................................................... 38
6.1 SOIC 16-Lead Package ............................................... 38
6.2 FAB024 24-Ball BGA Package .................................... 40
6.3 FAC024 24-Ball BGA Package.................................... 42
Software Interface
7. Address Space Maps................................................. 44
7.1 Overview....................................................................... 44
7.2 Flash Memory Array...................................................... 44
7.3 ID-CFI Address Space.................................................. 44
7.4 JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space............................................................... 45
7.5 OTP Address Space ..................................................... 45
7.6 Registers....................................................................... 47
8. Data Protection ........................................................... 57
8.1 Secure Silicon Region (OTP)........................................ 57
8.2 Write Enable Command................................................ 57
8.3 Block Protection............................................................ 58
8.4 Advanced Sector Protection ......................................... 59
9. Commands .................................................................. 63
9.1 Command Set Summary............................................... 64
9.2 Identification Commands .............................................. 70
9.3 Register Access Commands......................................... 72
9.4 Read Memory Array Commands .................................. 81
9.5 Program Flash Array Commands ................................. 95
9.6 Erase Flash Array Commands...................................... 98
9.7 One Time Program Array Commands ........................ 102
9.8 Advanced Sector Protection Commands.................... 103
9.9 Reset Commands ....................................................... 108
9.10 Embedded Algorithm Performance Tables................. 109
10. Data Integrity ............................................................. 110
10.1 Erase Endurance ........................................................ 110
10.2 Data Retention............................................................ 110
11. Software Interface Reference .................................. 111
11.1 Command Summary................................................... 111
11.2 Serial Flash Discoverable Parameters (SFDP) Address
Map............................................................................. 113
11.3 Device ID and Common Flash Interface (ID-CFI) Address
Map............................................................................. 117
11.4 Registers..................................................................... 136
11.5 Initial Delivery State .................................................... 139
12 Ordering Information................................................ 140
13. Revision History........................................................ 142
Document History Page.................................................... 142
Sales, Solutions, and Legal Information ......................... 145
Worldwide Sales and Design Support.......................... 145
Products ....................................................................... 145
PSoC® Solutions ......................................................... 145
Cypress Developer Community.................................... 145
Technical Support ........................................................ 145
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