没有合适的资源?快使用搜索试试~ 我知道了~
资源推荐
资源详情
资源评论
PCIe AMBA Integration Guide
Document number:
ARM DEN 0114
Release Quality:
ALP
Issue Number:
1.0
Confidentiality:
Non-Confidential
Date of Issue:
10/02/2022
© Copyright Arm Limited 2022. All rights reserved.
ARM DEN 0114 Copyright © 2022 Arm Limited or its affiliates. All rights reserved. Page ii
1.0 Non-Confidential
Contents
About this document v
Release Information v
References viii
Terms and abbreviations viii
Potential for change viii
Conventions viii
Typographical conventions viii
Numbers ix
Current status and anticipated changes ix
Feedback ix
Feedback on this book ix
1 Introduction 10
1.1 Introduction 10
2 Terminology 11
2.1 Transaction Terminology 11
2.2 Arm Terminology 11
2.2.1 Device memory 11
2.2.2 Normal memory 13
2.3 PCIe Terminology 15
2.3.1 Inbound and Outbound 16
3 ARM Memory Type USAGE FOR INBOUND AND OUTBOUND PCIE transactions 18
3.1 Memory Type Assumptions 18
3.2 Outbound Transaction Memory Type 18
3.3 Inbound Transaction Memory Type 19
3.3.1 Step 1: Determining the Arm memory type, cacheability and shareability attributes 19
3.3.2 Step 2: Modifying the cacheability attribute based on the transaction’s No Snoop bit value
19
3.3.3 Step 3: Mapping the Arm memory type, cacheability and shareability attributes to AXI/ACE
memory attributes. 20
ARM DEN 0114 Copyright © 2022 Arm Limited or its affiliates. All rights reserved. Page iii
1.0 Non-Confidential
3.3.4 Coherency management for Inbound transactions 20
4 COMPLYING TO ARM memory model FOR PE GENERATED PCIE TRANSACTIONs 23
4.1 Device-nGnRnE and Device-nGnRE 24
4.1.1 PE and Interconnect requirements for handling Outbound requests to Device-nGnRnE or
Device-nGnRE mapped locations 24
4.1.2 PCIe interface requirements for handling Outbound requests to Device-nGnRnE or Device-
nGnRE mapped locations 25
4.1.3 Example use cases for Device-nGnRnE and Device-nGnRE mapping of PCIe address spaces
25
4.2 Device-nGRE and Device-GRE 26
4.2.1 PCIe interface requirements for handling Outbound requests to Device-nGRE and Device-
GRE mapped locations 26
4.3 Normal with Non-cacheable as the cacheability attribute 27
4.3.1 PCIe interface requirements for handling Outbound requests to Normal Non-cacheable
mapped memory locations 27
4.4 Complying with internal visibility requirement of the Arm memory model 27
4.4.1 PCIe interface requirements for complying with internal visibility requirement for
Outbound transactions from PEs 28
4.5 PCIe interface requirements for handling transactions with the same AXI ID 28
4.6 Interconnect requirements for preserving barrier-ordered-before ordering relation 29
4.7 Setting RO and IDO for PE transactions 29
4.7.1 Setting RO for Root-SoC PE transactions 29
4.7.2 Setting IDO for Root-SoC PE transactions 29
4.7.3 Setting RO for Endpoint-SoC PE transactions 29
4.7.4 Setting IDO for Endpoint-SoC PE transactions 30
4.8 Ordering guarantees available to software for accesses targeting PCIe destinations 30
4.8.1 Achieving producer consumer ordering for transactions from PE to PCIe destinations 32
4.8.2 Multiple PCIe address spaces mapped as Device-nGnRnE or Device-nGnRE 33
5 COMPLYING TO PCIE ORDERING MODEL 34
5.1 Ordering table coverage 34
5.2 Overtaking and Ordering 36
5.3 Overtaking Rules 38
5.3.1 Both requests Outbound 38
5.3.2 Both requests Inbound 39
5.3.3 Outbound request / Inbound Completion 40
5.3.4 Outbound completion/ Inbound request 41
ARM DEN 0114 Copyright © 2022 Arm Limited or its affiliates. All rights reserved. Page iv
1.0 Non-Confidential
5.4 Ordering Rules 42
5.4.1 Both requests Outbound 42
5.4.2 Posted Write, Read Request, or Configuration Write must not overtake Posted Write [A2,
B2, C2] 42
5.4.3 Example Use Cases 43
5.4.4 Both requests Inbound 44
5.4.5 Outbound request/Inbound completion 47
5.4.6 Inbound request/Outbound completion 49
5.5 Ordering and overtaking rules - quick reference 52
5.6 IDO and RO for Outbound PCIe transactions 53
5.6.1 Root-SoC 53
5.6.2 Endpoint-SoC 53
6 Topology Considerations 54
6.1 Bridge Topology Considerations 54
6.1.1 Bridge A 54
6.1.2 Bridge B 55
6.2 IO Coherent PCIe Traffic 55
6.3 Intermediate Components 56
6.3.1 System MMU and PCIe Example 57
6.3.2 GIC and PCIe Example 57
ARM DEN 0114 Copyright © 2022 Arm Limited or its affiliates. All rights reserved. Page v
1.0 Non-Confidential
About this document
Release Information
The change history table lists the changes that have been made to this document.
Date
Version
Confidentiality
Change
Feb 2022
1.0
Non-Confidential
First release of 1.0 ALP version – This is a
comprehensive update of the 0.7 version dated
04/06/2013 (ARM-EPM-033524).
Key changes:
1. Updated the requirements to be in accordance
with the specifications listed in References
section.
2. Updated terminology to be in accordance with
the specifications listed in References section.
3. Added IDO and RO related recommendations
and requirements.
4. Restructured the content to bring all Arm
memory model related content into section 4
and all PCIe ordering model related content
into section 5.
剩余57页未读,继续阅读
资源评论
书香度年华
- 粉丝: 1w+
- 资源: 383
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功