/*
* File: ADRC.c
*
* Code generated for Simulink model 'ADRCSLX'.
*
* Model version : 1.3
* Simulink Coder version : 24.1 (R2024a) 19-Nov-2023
* C/C++ source code generated on : Thu Jun 20 23:25:04 2024
*
* Target selection: ert.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64)
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#include "ADRC.h"
#include <emmintrin.h>
#include "ADRCSLX.h"
#include "rtwtypes.h"
/* Output and update for atomic system: '<Root>/ADRC' */
void ADRCSLX_ADRC(void)
{
real_T tmp[3];
real_T UnitDelay_DSTATE;
real_T UnitDelay_DSTATE_0;
real_T UnitDelay_DSTATE_1;
real_T rtb_Subtract;
int32_T i;
/* Sum: '<S10>/Subtract' incorporates:
* Gain: '<S10>/Gain'
* Inport: '<Root>/In2'
* UnitDelay: '<S10>/Unit Delay'
*/
rtb_Subtract = ADRCSLX_U.In2 - ((0.0 * ADRCSLX_DW.UnitDelay_DSTATE[1] +
ADRCSLX_DW.UnitDelay_DSTATE[0]) + 0.0 * ADRCSLX_DW.UnitDelay_DSTATE[2]);
/* Outport: '<Root>/Out1' incorporates:
* Gain: '<S10>/Gain1'
* Gain: '<S9>/Gain2'
* Inport: '<Root>/In1'
* Sum: '<S10>/Add'
* Sum: '<S9>/Sum'
* Sum: '<S9>/Sum1'
* Sum: '<S9>/Sum2'
* UnitDelay: '<S10>/Unit Delay'
*/
ADRCSLX_Y.Out1 = ((ADRCSLX_U.In1 - (0.029554466451491623 * rtb_Subtract +
ADRCSLX_DW.UnitDelay_DSTATE[0])) - (0.29553973887722856 * rtb_Subtract +
ADRCSLX_DW.UnitDelay_DSTATE[1]) * 2.0) - (0.98512425356899236 * rtb_Subtract
+ ADRCSLX_DW.UnitDelay_DSTATE[2]);
/* UnitDelay: '<S10>/Unit Delay' incorporates:
* Gain: '<S10>/Gain2'
*/
UnitDelay_DSTATE = ADRCSLX_DW.UnitDelay_DSTATE[1];
UnitDelay_DSTATE_0 = ADRCSLX_DW.UnitDelay_DSTATE[0];
UnitDelay_DSTATE_1 = ADRCSLX_DW.UnitDelay_DSTATE[2];
/* Sum: '<S10>/Add1' incorporates:
* Gain: '<S10>/Gain2'
* Gain: '<S10>/Gain3'
* Gain: '<S10>/Gain4'
* Outport: '<Root>/Out1'
* UnitDelay: '<S10>/Unit Delay'
*/
for (i = 0; i <= 0; i += 2) {
_mm_storeu_pd(&tmp[i], _mm_add_pd(_mm_add_pd(_mm_add_pd(_mm_mul_pd
(_mm_loadu_pd(&ADRCSLX_ConstP.Gain2_Gain[i + 3]), _mm_set1_pd
(UnitDelay_DSTATE)), _mm_mul_pd(_mm_loadu_pd(&ADRCSLX_ConstP.Gain2_Gain[i]),
_mm_set1_pd(UnitDelay_DSTATE_0))), _mm_mul_pd(_mm_loadu_pd
(&ADRCSLX_ConstP.Gain2_Gain[i + 6]), _mm_set1_pd(UnitDelay_DSTATE_1))),
_mm_add_pd(_mm_mul_pd(_mm_loadu_pd(&ADRCSLX_ConstP.Gain3_Gain[i]),
_mm_set1_pd(ADRCSLX_Y.Out1)), _mm_mul_pd(_mm_loadu_pd
(&ADRCSLX_ConstP.Gain4_Gain[i]), _mm_set1_pd(rtb_Subtract)))));
}
for (i = 2; i < 3; i++) {
tmp[i] = ((ADRCSLX_ConstP.Gain2_Gain[i + 3] * UnitDelay_DSTATE +
ADRCSLX_ConstP.Gain2_Gain[i] * UnitDelay_DSTATE_0) +
ADRCSLX_ConstP.Gain2_Gain[i + 6] * UnitDelay_DSTATE_1) +
(ADRCSLX_ConstP.Gain3_Gain[i] * ADRCSLX_Y.Out1 +
ADRCSLX_ConstP.Gain4_Gain[i] * rtb_Subtract);
}
/* End of Sum: '<S10>/Add1' */
/* Update for UnitDelay: '<S10>/Unit Delay' */
ADRCSLX_DW.UnitDelay_DSTATE[0] = tmp[0];
ADRCSLX_DW.UnitDelay_DSTATE[1] = tmp[1];
ADRCSLX_DW.UnitDelay_DSTATE[2] = tmp[2];
}
/*
* File trailer for generated code.
*
* [EOF]
*/
