清华大学计算机系计算机组成原理课程大实验.zip

Release 14.7 - par P.20131013 (nt) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Thu Dec 01 20:15:43 2016 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: 1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. 2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. 3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator. INPUT FILE: CPU_map.ncd OUTPUT FILE: CPU_pad.txt PART TYPE: xc3s1200e SPEED GRADE: -4 PACKAGE: fg320 Pinout by Pin Number: +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |A1 | | |GND | | | | | | | | | | | | |A2 | | |TDI | | | | | | | | | | | | |A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | | |A4 | |DIFFM |IO_L24P_0 |UNUSED | |0 | | | | | | | | | |A5 | |DIFFMI |IP_L22P_0 |UNUSED | |0 | | | | | | | | | |A6 | |DIFFS |IO_L20N_0 |UNUSED | |0 | | | | | | | | | |A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |A8 |disp_g<2> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |A9 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |A10 | |DIFFS |IO_L12N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |A11 |inst<2> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |A12 |inst<8> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |A13 |inst<11> |IOB |IO_L05P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |A14 |inst<15> |IOB |IO_L04N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |A15 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | | |A16 |com_data_ready|IBUF |IO_L01N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |A17 | | |TCK | | | | | | | | | | | | |A18 | | |GND | | | | | | | | | | | | |B1 | | |PROG_B | | | | | | | | | | | | |B2 | | |GND | | | | | | | | | | | | |B3 | |DIFFS |IO_L25N_0/HSWAP |UNUSED | |0 | | | | | | | | | |B4 | |DIFFS |IO_L24N_0 |UNUSED | |0 | | | | | | | | | |B5 | |DIFFSI |IP_L22N_0 |UNUSED | |0 | | | | | | | | | |B6 | |DIFFM |IO_L20P_0 |UNUSED | |0 | | | | | | | | | |B7 | | |VCCAUX | | | | | | | |2.5 | | | | |B8 | |DIFFMI |IP_L13P_0/GCLK8 |UNUSED | |0 | | | | | | | | | |B9 |clk |IBUF |IP_L13N_0/GCLK9 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |B10 | |DIFFM |IO_L12P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |B11 |inst<3> |IOB |IO/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |B12 | | |VCCAUX | | | | | | | |2.5 | | | | |B13 |inst<12> |IOB |IO_L05N_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |B14 | |DIFFM |IO_L04P_0 |UNUSED | |0 | | | | | | | | | |B15 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | | |B16 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | |