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作为DesignCon 2024的获奖文章,本文演示如何使用一个2000A 阶跃电子负载对2000A PCB核心电源网络(PDN)设计进行有效验证。在此过程中,还需要进行可扩展的2000A供电网络的实际设计,包括并联电压转换器和多个控制回路,以此了解设计的权衡和挑战。并且,使用最新的基于测量的模型对转换器进行建模,然后使用最新的 EDA 仿真工具对瞬态、频率、EM、DC 和电热进行仿真,这对于节约硬件设备的采购资金投入是非常有意义的。另外,这种可扩展的 2000A PDN 设计还可用于演示带动态电流步进负载的核心电源的超高速测试,以验证大信号时域瞬态行为。
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Information Classification: General
Design, Simulation, and
Validation Challenges of a
Scalable 2000 Amp Core Power
Rail
Steve Sandler, Picotest.com
steve@picotest.com
Benjamin Dannan, Signal Edge Solutions
ben@signaledgesolutions.com
Heidi Barnes, Keysight Technologies
heidi_barnes@keysight.com
Idan Ben Ezra, Broadcom Semiconductors
idan.benezra@broadcom.com
Yu Ni, Monolithic Power Systems
Yu.Ni@monolithicpower.com
Information Classification: General
Abstract
The goal is to demonstrate how one can effectively validate a 2000 Amp core power rail
design using a substitute 2000 Amp step load device. In the process of doing this, it is
also necessary to go through an actual design of a scalable 2000 Amp power delivery
network (PDN) complete with parallel converters and multiple control loops to
understand the design trade-offs and challenges. Modeling of the converters using the
latest in measure-based models, and then simulating with the latest in EDA simulation
tools for transient, frequency, EM, DC, and electro-thermal are shown to be invaluable
for avoiding costly hardware re-spins and melted devices. The scalable 2000 Amp PDN
design can then be used to demonstrate the ultra-highspeed testing of a core power rail
with a dynamic current step-loader for validating large signal time domain transient
behavior.
Authors Biography
Steve Sandler Steve Sandler has been involved with power system engineering for more
than 40 years. Steve is the founder of PICOTEST.com, a Company specializing in power
integrity solutions, including measurement products, services, and training. He frequently
lectures and leads workshops internationally on the topics of power, PDN, and distributed
systems and is a Keysight-certified expert for EDA software. Steve frequently writes
articles and books related to power supply and PDN performance, and his latest book,
Power Integrity Using ADS, was published by Faraday Press in 2019. Steve founded AEi
Systems, a well-established leader in worst-case circuit analysis and troubleshooting of
high-reliability systems.
Benjamin Dannan Benjamin Dannan is the Chief Technologist at Signal Edge Solutions,
a senior member of IEEE, and an experienced signal and power integrity (SI/PI) design
consultant, advancing high-performance ASICs and developing advanced packaging
solutions for high-speed digital designs. He is a Keysight Certified Expert in ADS and
holds a certification in cybersecurity. He has a BSEE from Purdue University, a Master
of Engineering in Electrical Engineering from The Pennsylvania State University, and
graduated from the USAF Undergraduate Combat Systems Officer training school with
an aeronautical rating. Benjamin is a trained Electronic Warfare Officer in the USAF
with deployments on the EC-130J Commando Solo in Afghanistan and Iraq, totaling 47
combat missions, and a trained USAF Cyber Operations Officer. In addition, he has co-
authored multiple peer-reviewed journal publications on SI/PI-related topics and received
the prestigious DesignCon Best Paper award in 2020.
Heidi Barnes is a Senior Application Engineer for High-Speed Digital applications in the
EDA Group of Keysight Technologies. Her recent activities include the application of
electromagnetic, transient, and frequency domain simulators to solve power integrity
challenges. Author of over 20 papers on SI and PI and recipient of the DesignCon 2017
Engineer of the Year. Experience includes 11 years with Keysight SI and PI EDA
software, 6 years designing ATE test fixtures for Verigy, 6 years in RF/Microwave
microcircuit packaging for Agilent Technologies, and 10 years with NASA in the
Information Classification: General
aerospace industry. Heidi graduated in 1986 with a BSEE from the California Institute of
Technology.
Idan Ben Ezra Idan Ben Ezra is a Senior Hardware and PI engineer at Broadcom
Semiconductors, DNX group of CSG-Switch Products, in Israel. In Broadcom, Idan is a
focal point in full system Power Delivery Network analysis design stages. Developing PI
co-simulations and automation flow to cover corner cases (together & separate) for Board
(from VRM), Socket, Package & Interposer (Die with HBMs) - IR drop, PDN & Time
domain transient response simulation. Idan has hands-on experience with lab power
measurements, including correlation to simulation. In the past, he worked at Valens,
where he was instrumental as a board designer and as a simulation engineer for high-
speed automotive chips. Idan holds a Practical & a Bachelor (honors) in Electronics and
Computers Engineering from HIT, Israel.
Yu Ni is currently a supervisor for power module development with Monolithic Power
Systems, Inc., Chandler, AZ, USA, focusing on power module design and definitions. He
has been developing power conversion circuits and systems in the areas of aviation,
industry, and consumer electronics. He received a B.S. degree in electrical engineering
from Xi'an Jiaotong University, Xi'an, China, in 2012 and an M.S. degree in electrical
engineering from the University of Colorado Boulder, Boulder, in 2014.
Information Classification: General
Introduction
Designing a power distribution network (PDN) for a scalable 2000 Amp power supply
presents numerous challenges. This paper will address these challenges while
demonstrating how to design, simulate, and validate a scalable core power rail with a
current of 2000 Amp. The most common architectures for high-current power rails utilize
a 48 VDC input to reduce the current to a more manageable level. This 48 VDC input is
then pulse width modulated (PWM) and supplied to multiple parallel unregulated
resonant DC-DC converter modules to output the ASIC core supply voltage.
Alternatively, the 48VDC could be stepped down to an intermediate 5VDC or 12VDC
with multiple parallel unregulated resonant DC-DC converter modules and then go
through parallel multi-phase PWM switches to regulate the voltage down to the core
voltage. Choosing the appropriate architecture involves various tradeoffs, with the small
signal and large signal control loop responses being particularly significant. Current
sharing between parallel converters is also a crucial consideration, involving the layout
symmetry of the printed circuit board and communication between power modules and a
central controller. These tradeoffs are typically addressed through simulation and the use
of cascaded power stages requires additional simulator support that was previously
unavailable.
This paper also examines additional layout considerations. For instance, clean voltage
sense traces are usually included to convey the operating voltage in close proximity to or
even on the ASIC package. However, it is critical through simulation and measurement to
verify the noise on the sense lines and determine the significance of any crosstalk with
the nearby 2000 Amp switching load. Further, the methodology for measuring and
validating the quality of the output current from a 2000 Amp power supply is
complicated and challenging. Loading the power rail to the peak power limit of the ASIC
is necessary, but if the ASIC is not yet available then a substitute load stepper device
must be devised for early testing of the PCB PDN. Additionally, utilizing the ASIC as a
litmus test for an adequate power rail design can be costly. Evaluating the large signal
response requires dynamically modulating the power rail with an edge speed
representative of the ASIC package limit, typically around 100MHz or a rise/fall time of
about 3ns. While achieving high-current, high-speed modulation is challenging, it is also
essential that the measurement of the dynamic current does not impede the dynamic edge.
This paper comprehensively addresses these topics and provides a complete process for
designing, simulating, and validating a 2000 Amp core power rail. The process involves
utilizing a custom-designed evaluation board with a refrigeration-cooled ultra-high-speed
in-socket load that is all designed with the latest in power integrity simulation software.
The scalable 2000 Amp design is shown operating at 256 Amps in Figure 1.
Information Classification: General
Figure 1: Successful water cooled 256 Amp Step Load in operation.
Why do we need 2000 Amps for digital electronics?
While 2000 Amps may seem excessive, the increasing processing power of AI, data
centers, and supercomputing has already exceeded this current level. The NVIDIA H100
Tensor Core GPU for AI applications is about 750 Amps, but it is expected that the next
generation X100 will require about 1500 Amps. These operating currents are high, but
this is just the result of technological growth. The exponential expansion of 3.2T 224G
SerDes transceivers also contributes to this increased operating current. We can expect
that this current will continue to increase as technology innovation demands increased
computing power.
Some companies are evaluating the distribution of the 2000 Amps across multiple chips
to reduce the current per die. While this concept may be interesting, the total current still
adds up to 2000 Amps but adds additional cost. One engineer who believed that the 2000
Amp power rail was aiming a bit high was surprised to learn that his next project is 2000
Amps.
The 2000 Amps is just a magnitude. There are other considerations, including the
thermal design, parasitic inductance in the PDN, the projected dynamic current, and the
bandwidth of the current from the package, including the effects of the package and die
filtering.
Several vendors have developed scalable VRM solutions so that they can economically
support much lower current applications, as low as 150 Amps to 200 Amps while
offering scalability to above 2000 Amps. Each of the vendors has chosen a different
topology for their solution, and so now we’ll consider the topological options.
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