• RTL8231_Datasheet_1.1.pdf

    SMI SLAVE/MIIM/SHIFT REGISTER LED DISPLAY CONTROLLER

    5
    959
    1.54MB
    2021-08-14
    49
  • AltiumLL2v20.zip

    Altium Library Loader 2.2最新版本,老版本需要升级到2.2版本才能下载库

    0
    184
    1.15MB
    2021-03-15
    40
  • Altium Library Loader 1.9 Setup

    Altium Library Loader 1.9 Setup 最新版,实测可用

    0
    631
    1.15MB
    2020-12-23
    50
  • Hi3521DV100DMEB_VER_B_PCB Altium Designer版

    Hi3521DV100DMEB_VER_B_PCB 海思原厂DEMO PCB板Altium Designer版本

    0
    109
    1.09MB
    2020-11-12
    16
  • Hi3521DV100DMEB_VER_B_SCH Altium Designer版本

    Hi3521DV100DMEB_VER_B_SCH Altium Designer版本原厂DEMO硬件原理图

    0
    156
    860KB
    2020-11-12
    16
  • HI3519AV100LPDDR4TB_VER_B_PCB.PcbDoc

    海思HI3519AV100LPDDR4TB_VER_B_PCB官方参考设计,转Altium Designer版本

    0
    379
    26.79MB
    2020-05-08
    33
  • MT53E256M16D1.pdf

    LPDDR4/LPDDR4X SDRAM,MT53E256M16D1, MT53E256M32D2,LPDDR4/LPDDR4X SDRAM MT53E256M16D1, MT53E256M32D2 Features This data sheet is for LPDDR4 and LPDDR4X unified product based on LPDDR4X information. Refer to LPDDR4 setting section LPDDR4 1.10V VDDQ at the end of this data sheet. • Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70–1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal – VDDQ = 1.06–1.17V; 1.10V nominal or Low VDDQ = 0.57–0.65V; 0.60V nominal • Frequency range – 1866–10 MHz (data rate range: 3733–20 Mbps/ pin) • 16n prefetch DDR architecture • 8 internal banks per channel for concurrent operation • Single-data-rate CMD/ADR entry • Bidirectional/differential data strobe per byte lane • Programmable READ and WRITE latencies (RL/WL) • Programmable and on-the-fly burst lengths (BL = 16, 32) • Directed per-bank refresh for concurrent bank operation and ease of command scheduling • Up to 8.5 GB/s per die • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Selectable output drive strength (DS) • Clock-stop capability • RoHS-compliant, “green” packaging • Programmable VSS (ODT) termination

    0
    719
    4.08MB
    2020-03-09
    50
  • MT53B256M32D1NP.pdf

    Mobile LPDDR4 SDRAM,MT53B256M32D1, MT53B512M32D2, MT53B1024M32D4,Features • Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70–1.95V; 1.8V nominal – VDD2/VDDQ = 1.06–1.17V; 1.10V nominal • Frequency range – 1600–10 MHz (data rate range: 3200–20 Mb/s/ pin) • 16n prefetch DDR architecture • 2-channel partitioned architecture for low RD/WR energy and low average latency • 8 internal banks per channel for concurrent operation • Single-data-rate CMD/ADR entry • Bidirectional/differential data strobe per byte lane • Programmable READ and WRITE latencies (RL/WL) • Programmable and on-the-fly burst lengths (BL = 16, 32) • Directed per-bank refresh for concurrent bank operation and ease of command scheduling • Up to 12.8 GB/s per die (2 channels x 6.4 GB/s) • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Selectable output drive strength (DS) • Clock-stop capability • RoHS-compliant, “green” packaging • Programmable VSSQ (ODT) termination

    0
    1016
    3.99MB
    2020-02-25
    50
  • RTL8153B-VB-CG_REALTEK.pdf

    INTEGRATED 10/100/1000M ETHERNETCONTROLLER FOR USB 3.0 APPLICATIONS

    0
    1025
    672KB
    2020-02-21
    50
  • IMX291LQR-C-Sony.pdf

    IMX291LQR-C Image Sensor MIPI接口 datasheet The IMX291LQR-C is a diagonal 6.46 mm (Type 1/2.8) CMOS active pixel type solid-state image sensor with a square pixel array and 2.13 M effective pixels. This chip operates with analog 2.9 V, digital 1.2 V, and interface 1.8 V triple power supply, and has low power consumption. High sensitivity, low dark current and no smear are achieved through the adoption of R, G and B primary color mosaic filters. This chip features an electronic shutter with variable charge-integration time. (Applications: Surveillance cameras, FA cameras, Industrial cameras)

    0
    405
    1.51MB
    2020-02-21
    12
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