TMS320C6657例程程序

Initialize DSP main clock = 100.00MHz/1x10 = 1000MHz SRIO path configuration 4xLaneABCD Enable Exception handling... ====================L1P ED test================================= !!!manually generate one bit error in L1P cache for function at 0x8008a0, and then execute it... internal excpetion happened. IERR=0x9. Instruction fetch exception Opcode exception L1P Cache parity check error caused by program fetch at address 0x8008a0 NRP=0x800882, NTSR=0x1000d, IRP=0x0, ITSR=0x0, TSCH= 0x0, TSCL= 0x4d9267ad B3=0xc0138e8, A4=0x1846408, B4= 0x1840024, B14= 0x829c40, B15= 0x828f78 !!!manually generate one bit error in L1P cache at 0xe008a0, and then read it by DMA... External exception happened. MEXPFLAG[3]=0x20000. Event 113: PMC_ED Single bit error detected during DMA read L1P RAM parity check error caused by DMA at address 0xe008a0 NRP=0xc013950, NTSR=0x1000d, IRP=0x0, ITSR=0x0, TSCH= 0x0, TSCL= 0x4d939a90 B3=0xc013944, A4=0xe00880, B4= 0x1820100, B14= 0x829c40, B15= 0x828f78 ===================-LL2 EDC test-================================ --------------------LL2 data EDC test---------------------------- !!!manually generate 3 bit error in data at 0x829da8, and then read it... External exception happened. MEXPFLAG[3]=0x200000. Event 117: UMC_ED2 Uncorrected bit error detected LL2 EDC error (non-correctable) at address 0x829da0 caused by L1D access. total non-correctable error number= 1, total correctable error number= 0. NRP=0xc00eba0, NTSR=0x1000d, IRP=0x0, ITSR=0x0, TSCH= 0x0, TSCL= 0x4d94bd05 B3=0xc00eb84, A4=0x1846008, B4= 0x7, B14= 0x829c40, B15= 0x828f70 !!!manually generate 2 bit error in data at 0x829da8, and then read it... External exception happened. MEXPFLAG[3]=0x200000. Event 117: UMC_ED2 Uncorrected bit error detected LL2 EDC error (non-correctable) at address 0x829da0 caused by L1D access. total non-correctable error number= 2, total correctable error number= 0. NRP=0xc00ec14, NTSR=0x1000d, IRP=0x0, ITSR=0x0, TSCH= 0x0, TSCL= 0x4d960cb6 B3=0xc00ebfa, A4=0x829d80, B4= 0x1840044, B14= 0x829c40, B15= 0x828f70 !!!manually generate one bit error in data at 0x829da8, and then read it... External exception happened. MEXPFLAG[3]=0x200000. Event 117: UMC_ED2 Uncorrected bit error detected LL2 EDC error (non-correctable) at address 0x829da0 caused by L1D access. total non-correctable error number= 3, total correctable error number= 0. NRP=0xc00ec88, NTSR=0x1000d, IRP=0x0, ITSR=0x0, TSCH= 0x0, TSCL= 0x4d975eb1 B3=0xc00ec72, A4=0x1846008, B4= 0x1, B14= 0x829c40, B15= 0x828f70 !!!scrub the corrupted data to fix the error... LL2 EDC (correctable) at bit 88 of address 0x829da0 caused by DMA access. total non-correctable error number= 3, total correctable error number= 1. IRP= 0xc00ece6, ITSR= 0xd. TSCH= 0x0, TSCL= 0x4d987fa5 read the data again...(no error happens again) --------------------LL2 code EDC test---------------------------- !!!manually generate one bit error in a function at 0x8007a0, and then execute the function... LL2 EDC (correctable) at bit 13 of address 0x8007a0 caused by L1P access. total non-correctable error number= 3, total correctable error number= 3. IRP= 0x800786, ITSR= 0xd. TSCH= 0x0, TSCL= 0x4d9975cf one bit error was corrected with previous execution. Execute the function again...(no error happens again) ===================-SL2 EDC test-================================ !!!manually generate one bit error in a function at 0xc017800, and then execute the function... SL2 Correctable error occurred at bit 237 of address 0xc017800 by PrivID 0 (from C66x CorePacs) IRP= 0xc0177f8, ITSR= 0xd. TSCH= 0x0, TSCL= 0x4d9a8641 one bit error was corrected with previous execution. Execute the function again...(no error happens again) !!!manually generate one bit error data at 0xc08d000, and then read it... SL2 Correctable error occurred at bit 240 of address 0xc08d000 by PrivID 0 (from C66x CorePacs) IRP= 0xc00f5b0, ITSR= 0xf. TSCH= 0x0, TSCL= 0x4d9b47dd !!!manually generate one bit error data at 0xe0000000, and then read it... SL2 Correctable error occurred at bit 240 of address 0xc08d000 by PrivID 0 (from C66x CorePacs) IRP= 0xc00f5b0, ITSR= 0xf. TSCH= 0x0, TSCL= 0x4d9c03b4 test complete.