DS558 March 1, 2011 www.xilinx.com 1
Product Specification
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Introduction
The LogiCORE™ IP DDS (Direct Digital Synthesizer)
Compiler core sources sinusoidal waveforms for use in
many applications. A DDS consists of a Phase Generator
and a SIN/COS Lookup Table. These parts are available
individually or combined via this core.
Features
• Drop-in module for Kintex™-7, Virtex
®
-7, Virtex-6,
Virtex-5, Virtex-4, Spartan
®
-6, Spartan-3/XA,
Spartan-3E/XA and Spartan-3A/AN/3A DSP/XA
FPGAs
• Phase Generator and SIN/COS Lookup Table can be
generated independently or combined together with
optional Dither circuit to provide complete DDS solution
• High speed, including optimal and optional use of
XtremeDSP
™
slice
• Sine, Cosine, or quadrature outputs
• Lookup table can be allocated to distributed or block
memory
• A phase dithering option spreads the spectral line
energy structure associated with conventional phase
truncation waveform synthesis architectures
• Phase dithering or Taylor series correction options
provide high dynamic range signals using minimal
FPGA resources. Supports Spurious Free Dynamic
Range (SFDR) from 18 dBs to 150 dBs
• Support for 1 to 16 independent time-multiplexed
channels
•
Optional channel output indication for multi-channel use
• High-precision synthesizer with fine frequency
resolution using up to 48-bit phase accumulator with
XtremeDSP slice or fabric options
•
3-bit to 26-bit two’s complement output sample precision
• Optional phase offset capability allows multiple
synthesizers with precisely controlled phase differences
• Frequency and phase offset may be independently
configured as constant, programmable or dynamic (for
modulation)
• Choice of amplitude modes allows either maximal use of
output dynamic range or unit circle amplitude
• Optional inversion of Sine or Cosine outputs
• GUI entry selectable in terms of System (SDFR and
frequency resolution) or Hardware (phase and output
width) parameters.
• For use with Xilinx CORE Generator™ software v13.1
LogiCORE IP DDS Compiler v4.0
DS558 March 1, 2011 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
1. For a complete listing of supported devices, see the release notes
for this core.
Virtex-7 and Kintex-7,
Virtex-6, Virtex-5, Virtex-4,
Spartan-6, Spartan-3/XA, Spartan-3E/XA,
Spartan-3A/3AN/3A DSP/XA
Supported User
Interfaces
Not Applicable
Resources
(2)
2. Resources listed here are for Virtex-6 devices. For more complete
device performance numbers, see Table 6 - Table 13.
Frequency
Configuration LUTs FFs
DSP
Slices
Block
RAMs
(3)
3. Based on 18K block RAMs (or 36K - select appropriate size).
Max.
Freq.
(4)
4. Performance numbers listed are for Virtex-6 FPGAs. For more
complete performance data, see Performance and Resource
Utilization, page 25.
SFDR70, 12-bit
phase, 12-bit
sin/cos output,
use DSP48
71 131 1 1 400 MHz
Provided with Core
Documentation
Product Specification
Design Files Netlist
Example Design Not Provided
Test Bench Not Provided
Constraints File Not Applicable
Simulation
Model
VHDL behavioral model in the xilinxcorelib library
VHDL UniSim structural model
Verilog UniSim structural model
Tested Design Tools
Design Entry
Tools
CORE Generator tool 13.1
System Generator for DSP 13.1
Simulation
Mentor Graphics ModelSim 6.6d
Cadence Incisive Enterprise Simulator (IES) 10.2
Synopsys VCS and VCS MX 2010.06
ISIM 13.1
Synthesis Tools N/A
Support
Provided by Xilinx, Inc.
