基于xilinx的dds信号发生器源码
1：顶层模块
module dds(
clk,
rstn,
key,
key1,
key2,
douta,
smgen,
smgdat,
clk400
);
input clk;
input key;
input key1;
input key2;
input rstn;
output reg [11:0] douta;
output wire [7:0] smgen;
output wire [0:7] smgdat;
output wire clk400;
wire [11:0] douta1;
wire [11:0] douta2;
wire [11:0] douta3;
wire [22:0] xianshi;
wire flag1;
wire flag2;
wire flag;
wire ena=1;
wire [9:0] addra;
reg [2:0] boxing;
reg [2:0] weien;
reg [3:0] ge;
reg [3:0] shi;
reg [3:0] bai;
reg [2:0] qian;
reg [3:0] wan;
reg [3:0] shiwan;
reg [3:0] baiwan;
always @ (posedge clk or negedge rstn)
if(!rstn)
boxing<=0;
else
if(flag==1)
boxing<=boxing+1;
else if(boxing==4)
boxing<=1;
always @ (posedge clk or negedge rstn)
if(!rstn)
douta<=0;
else
case(boxing)
1:
douta<=douta1;
2:
douta<=douta2;
3:
douta<=douta3;
