STM32USB固件库

/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** * File Name : otgd_fs_cal.c * Author : STMicroelectronics * Version : V3.2.1 * Date : 07/05/2010 * Description : OTG FS Device Core Access Layer interface. ******************************************************************************** * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *******************************************************************************/ #ifdef STM32F10X_CL /* Includes ------------------------------------------------------------------*/ #include "otgd_fs_cal.h" #include "usb_conf.h" #include "otgd_fs_regs.h" /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ USB_OTG_CORE_REGS USB_OTG_FS_regs; /* Private function prototypes -----------------------------------------------*/ static USB_OTG_Status OTGD_FS_SetDeviceMode(void); static USB_OTG_Status OTGD_FS_CoreReset(void); extern uint32_t STM32_PCD_OTG_ISR_Handler (void); /******************************************************************************/ /* Common Core Layer */ /******************************************************************************/ /******************************************************************************* * Function Name : OTGD_FS_WritePacket * Description : Writes a packet into the Tx FIFO associated with the EP * Input : None * Output : None * Return : Status *******************************************************************************/ USB_OTG_Status OTGD_FS_WritePacket(uint8_t *src, uint8_t ep_num, uint16_t bytes) { USB_OTG_Status status = USB_OTG_OK; uint32_t dword_count = 0 , i = 0; __IO uint32_t *fifo; /* Find the DWORD length, padded by extra bytes as neccessary if MPS * is not a multiple of DWORD */ dword_count = (bytes + 3) / 4; fifo = USB_OTG_FS_regs.FIFO[ep_num]; for (i = 0; i < dword_count; i++, src += 4) { USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); } return status; } /******************************************************************************* * Function Name : OTGD_FS_ReadPacket * Description : Reads a packet from the Rx FIFO * Input : None * Output : None * Return : status *******************************************************************************/ void* OTGD_FS_ReadPacket(uint8_t *dest, uint16_t bytes) { uint32_t i = 0; uint32_t word_count = (bytes + 3) / 4; __IO uint32_t *fifo = USB_OTG_FS_regs.FIFO[0]; uint32_t *data_buff = (uint32_t *)dest; for (i = 0; i < word_count; i++, data_buff++) { *data_buff = USB_OTG_READ_REG32(fifo); } /* Return the buffer pointer because if the transfer is composed of several packets, the data of the next packet must be stored following the previous packet's data */ return ((void *)data_buff); } /******************************************************************************* * Function Name : OTGD_FS_SetAddress * Description : Initialize core registers addresses. * Input : BaseAddress * Output : None * Return : status *******************************************************************************/ USB_OTG_Status OTGD_FS_SetAddress(uint32_t BaseAddress) { uint32_t i = 0; USB_OTG_Status status = USB_OTG_OK; USB_OTG_FS_regs.GREGS = (USB_OTG_GREGS *)(BaseAddress +\ USB_OTG_CORE_GLOBAL_REGS_OFFSET); USB_OTG_FS_regs.DEV = (USB_OTG_DEV *) (BaseAddress +\ USB_OTG_DEV_GLOBAL_REG_OFFSET); for (i = 0; i < NUM_TX_FIFOS; i++) { USB_OTG_FS_regs.DINEPS[i] = (USB_OTG_DINEPS *) (BaseAddress + \ USB_OTG_DEV_IN_EP_REG_OFFSET + (i * USB_OTG_EP_REG_OFFSET)); USB_OTG_FS_regs.DOUTEPS[i] = (USB_OTG_DOUTEPS *) (BaseAddress + \ USB_OTG_DEV_OUT_EP_REG_OFFSET + (i * USB_OTG_EP_REG_OFFSET)); } for (i = 0; i < NUM_TX_FIFOS; i++) { USB_OTG_FS_regs.FIFO[i] = (uint32_t *)(BaseAddress + \ USB_OTG_DATA_FIFO_OFFSET + (i * USB_OTG_DATA_FIFO_SIZE)); } USB_OTG_FS_regs.PCGCCTL = (uint32_t *)(BaseAddress + USB_OTG_PCGCCTL_OFFSET); return status; } /******************************************************************************* * Function Name : OTGD_FS_CoreInit * Description : Initialize the USB_OTG controller registers and prepares the core for device mode or host mode operation. * Input : None * Output : None * Return : Status *******************************************************************************/ USB_OTG_Status OTGD_FS_CoreInit(void) { USB_OTG_Status status = USB_OTG_OK; USB_OTG_GUSBCFG_TypeDef usbcfg; USB_OTG_GCCFG_TypeDef gccfg; usbcfg.d32 = 0; gccfg.d32 = 0; usbcfg.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.GREGS->GUSBCFG); usbcfg.b.physel = 1; USB_OTG_WRITE_REG32 (&USB_OTG_FS_regs.GREGS->GUSBCFG, usbcfg.d32); /* init and configure the phy */ gccfg.d32 = 0; gccfg.b.vbussensingB = 1; gccfg.b.pwdn = 1; USB_OTG_WRITE_REG32 (&USB_OTG_FS_regs.GREGS->GCCFG, gccfg.d32); mDELAY(50); /* Reset after a PHY select and set Host mode */ OTGD_FS_CoreReset(); /* Set Device Mode */ OTGD_FS_SetDeviceMode(); return status; } /******************************************************************************* * Function Name : OTGD_FS_CoreReset * Description : Soft reset of the core * Input : None * Output : None * Return : Status *******************************************************************************/ static USB_OTG_Status OTGD_FS_CoreReset(void) { USB_OTG_Status status = USB_OTG_OK; __IO USB_OTG_GRSTCTL_TypeDef greset; uint32_t timeout = 0; greset.d32 = 0; /* Wait for AHB master IDLE state. */ do { uDELAY(5); greset.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.GREGS->GRSTCTL); if (++timeout > USB_OTG_TIMEOUT) { return USB_OTG_OK; } } while (greset.b.ahbidle == 0); /* Core Soft Reset */ timeout = 0; greset.b.csftrst = 1; USB_OTG_WRITE_REG32(&USB_OTG_FS_regs.GREGS->GRSTCTL, greset.d32 ); do { greset.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.GREGS->GRSTCTL); if (++timeout > USB_OTG_TIMEOUT) { break; } } while (greset.b.csftrst == 1); /* Wait for 3 PHY Clocks*/ uDELAY(5); return status; } /******************************************************************************* * Function Name : OTGD_FS_EnableGlobalInt * Description : Enables the controller's Global Int in the AHB Config reg * Input : None * Output : None * Return : Status *******************************************************************************/ USB_OTG_Status OTGD_FS_EnableGlobalInt(void) { USB_OTG_Status status = USB_OTG_OK; USB_OTG_GAHBCFG_TypeDef ahbcfg; ahbcfg.d32 = 0; ahbcfg.b.gintmsk = 1; /* Enable interrupts */ USB_OTG_MODIFY_REG32(&USB_OTG_FS_regs.GREGS->GAHBCFG, 0, ahbcfg.d32); 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