i.MX 6Dual/6Quad Applications
Processor Reference Manual
Document Number: IMX6DQRM
Rev. 0, 11/2012
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 0, 11/2012
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
Introduction
1.1 About This Document...................................................................................................................................................193
1.1.1 Audience....................................................................................................................................................193
1.1.2 Organization...............................................................................................................................................193
1.1.3 Suggested Reading.....................................................................................................................................194
1.1.3.1 General Information...............................................................................................................194
1.1.3.2 Related Documentation..........................................................................................................194
1.1.4 Conventions...............................................................................................................................................194
1.1.5 Register Access..........................................................................................................................................196
1.1.5.1 Register Diagram Field Access Type Legend........................................................................196
1.1.5.2 Register Macro Usage............................................................................................................196
1.1.6 Signal Conventions....................................................................................................................................197
1.1.7 Acronyms and Abbreviations.....................................................................................................................198
1.2 Introduction...................................................................................................................................................................199
1.3 Target Applications.......................................................................................................................................................200
1.4 Features.........................................................................................................................................................................200
1.5 Architectural Overview.................................................................................................................................................204
1.5.1 Block Diagram...........................................................................................................................................204
1.5.1.1 Simplified Block Diagram.....................................................................................................204
1.5.2 Architectural Partitioning...........................................................................................................................205
1.5.3 Endianness Support....................................................................................................................................207
1.5.4 Memory Interfaces.....................................................................................................................................207
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................209
2.2 ARM platform memory map........................................................................................................................................209
2.3 DDR mapping to MMDC controller ports....................................................................................................................215
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Section number Title Page
2.4 DMA memory map.......................................................................................................................................................216
Chapter 3
Interrupts and DMA Events
3.1 Overview.......................................................................................................................................................................219
3.2 AP interrupts.................................................................................................................................................................219
3.3 SDMA event mapping..................................................................................................................................................223
Chapter 4
External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................227
4.1.1 Pin Assignments.........................................................................................................................................227
4.1.2 Muxing Options.........................................................................................................................................304
Chapter 5
Fusemap
5.1 Fusemap........................................................................................................................................................................347
5.2 Fusemap Description Table..........................................................................................................................................356
Chapter 6
External Memory Controllers
6.1 Overview.......................................................................................................................................................................363
6.2 Multi-mode DDR controller (MMDC) overview and feature summary......................................................................363
6.3 Raw NAND Flash controller overview.........................................................................................................................365
6.3.1 NAND interface features...........................................................................................................................366
6.3.2 NAND control features..............................................................................................................................367
6.3.3 Internal interface features...........................................................................................................................367
6.3.4 APBH-DMA overview..............................................................................................................................367
6.3.5 ECC-BCH features.....................................................................................................................................367
6.4 EIM-PSRAM/NOR Flash controller overview.............................................................................................................368
6.4.1 EIM features...............................................................................................................................................368
6.4.2 EIM boot scenarios....................................................................................................................................369
6.4.3 EIM boot configuration..............................................................................................................................369
6.4.4 OneNAND requirements............................................................................................................................369
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 0, 11/2012
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Section number Title Page
Chapter 7
System Debug
7.1 Overview.......................................................................................................................................................................371
7.2 Chip and Cortex-A9 Core Platform Debug Architecture.............................................................................................371
7.2.1 Debug Features..........................................................................................................................................372
7.2.2 Debug System components........................................................................................................................373
7.2.2.1 AMBA trace bus (ATB).........................................................................................................374
7.2.2.2 ATB replicator.......................................................................................................................374
7.2.2.3 Embedded Cross Triggering..................................................................................................374
7.2.2.3.1 Cross-Trigger Matrix (CTM)..........................................................................375
7.2.2.3.2 Cross-Trigger Interface (CTI).........................................................................376
7.2.2.4 Debug Access Port (DAP).....................................................................................................376
7.2.2.5 CoreSight trace port interface (TPIU)....................................................................................377
7.2.3 i.MX6Dual/6Quad-Specific SJC Features.................................................................................................378
7.2.3.1 JTAG Disable Mode..............................................................................................................378
7.2.3.2 JTAG ID.................................................................................................................................378
7.2.4 System JTAG Controller - SJC..................................................................................................................379
7.2.5 System JTAG controller main features......................................................................................................379
7.2.6 SCJ TAP Port.............................................................................................................................................379
7.2.7 SJC main blocks.........................................................................................................................................379
7.3 Smart DMA (SDMA) core............................................................................................................................................380
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary...............................................................381
7.3.1.1 Other SDMA Debug Functionality........................................................................................381
7.3.1.2 SDMA ROM Patching...........................................................................................................382
7.4 Miscellaneous...............................................................................................................................................................382
7.4.1 Clock/Reset/Power.....................................................................................................................................382
7.5 Supported tools.............................................................................................................................................................383
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